DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The following title is suggested: SEMICONDUCTOR DEVICE HAVING DEEP TRENCH CAPACITOR AND METHOD FOR MAKING SAME.
Claim Objections
Claim 17 is objected to because of the following informalities: Line 1 of claim 17 reads in part “17. The semiconductor device of claim 14”. However, claim 14 is a method claim depending from independent method claim 11. Therefore, for examination purposes, and consistency with claims 11 and 14, “17. The semiconductor device of claim 14” will be interpreted to read as “17. The method of claim 14”. Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claims 4-5 and 15-16 are rejected under 35 U.S.C. 112(b), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
A. Claim 4 recites the limitation "the conductive material layer" in lines 4-5 and "the conductive material layer is electrically isolated" in line 6. There is insufficient antecedent basis for these limitations in the claim.
For examination purposes, "the conductive material layer" in lines 4-5 and "the conductive material layer is electrically isolated" in line 6 will be interpreted to read as "the at least two conductive material layers" and "the at least two conductive material layers are electrically isolated", respectively.
Further, claim 5 is rejected since it depends from claim 4, and requires all of the limitations of 122(b) rejected claim 4.
B. Claim 5 recites "the conductive material layers" in lines 4-5 and "the conductive material layers" in line 8. There is insufficient antecedent basis for these limitations in the claim.
For examination purposes, "the conductive material layers" in lines 4-5 and "the conductive material layers" in line 8 will be interpreted to read as "the at least two conductive material layers" in lines 4-5 and "the at least two conductive material layers", respectively.
C. Claim 15 recites the limitation "the conductive material layer" in line 6 and "the conductive material layer is electrically isolated" in lines 7-8. There is insufficient antecedent basis for these limitations in the claim.
For examination purposes, "the conductive material layer" in line 6 and "the conductive material layer is electrically isolated" in lines 7-8 will be interpreted to read as "the at least two conductive material layers" and "the at least two conductive material layers are electrically isolated", respectively.
Further, claim 16 is rejected since it depends from claim 15, and requires all of the limitations of 122(b) rejected claim 15.
D. Claim 16 recites "the conductive material layers" in line 6 and "the conductive material layers" in line 8. There is insufficient antecedent basis for these limitations in the claim.
For examination purposes, "the conductive material layers" in line 6 and "the conductive material layers" in line 8 will be interpreted to read as "the at least two conductive material layers" and "the at least two conductive material layers", respectively.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-4, 6-10; 11-12 and 15 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by CHANG et al (US 2023/0069315 A1, hereafter Chang).
Re claim 1, Chang discloses in FIGS. 1A-1C a semiconductor device, comprising: a first substrate (202; [0040]) comprising a front side (first side; [0041]) and a backside (unlabeled second side) opposite to (below) the front side (first side), wherein a device structure (integrated circuit region comprising gate electrodes 204; [0042]) is formed at the front side (first side) of the first substrate (202), and a deep trench capacitor (DTC 500; [0069]) is formed at the backside (unlabeled second side) of the first substrate (202);
a first insulating layer (IMD layers 214 of 210; [0040]-[0041]) and a second insulating layer (IMD layers 314 of 310; [0048]-[0049]), which are formed on the front side (first side) and the backside (unlabeled second side) of the first substrate (202), respectively;
a first interconnect structure (metal features 216 of 210; [0041]-[0042]) and a second interconnect structure (metal features 316 of 310; [0049]), wherein the first interconnect structure (metal features 216 of 210) is formed in the first insulating layer (IMD layers 214 of 210), and the second interconnect structure (metal features 316 of 310) is formed in the second insulating layer (IMD layers 314 of 310); and
a plug structure (250; [0045]) formed in the first insulating layer (IMD layers 214 of 210), wherein a first end (bottom) of the plug structure (250) is electrically connected (for device interconnectivity and operation; [0042] and [0045]) to the device structure (integrated circuit region comprising gate electrodes 204) through the first interconnect structure (metal features 216 of 210), and a second end (top) of the plug structure (250) is electrically connected (through 332 for device interconnectivity and operation; [0050] and [0074]-[0076]) to the DTC (500) through the second interconnect structure (metal features 316 of 310).
For the record, the examiner is interpreting the expression “electrically connected” to include direct and indirect connections between features for device operation.
Re claim 2, Chang discloses the semiconductor device of claim 1, wherein the plug structure (250) extends from the first insulating layer (IMD layers 214 of 210) into the first substrate (202), and further extends through (as a TSV; [0045]) the first substrate (202).
Re claim 3, Chang discloses the semiconductor device of claim 1, wherein an end surface (bottom plane) of the plug structure (250) located within the first insulating layer (IMD layers 214 of 210) is in a same layer (an IMD layer 214 of 210 at 250/216 interface) as any one of conductive layers (metal feature 216 at 250) in the first interconnect structure (metal features 216 of 210).
Re claim 4, Chang discloses the semiconductor device of claim 1,wherein the DTC (500) comprises: a stack of at least two conductive material layers (502/504; [0071]) and at least one dielectric material layer (506; [0071]) located between adjacent conductive material layers (502/504), which are formed in a deep trench (T; [0080]) in the backside (unlabeled second side) of the first substrate (202), wherein the at least two conductive material layers (502/504) and the dielectric material layer (506) further extend to the backside (unlabeled second side) of the first substrate (202) around (surrounding and filling) the deep trench (T), and wherein the at least two conductive material layers (502/504) are electrically isolated (by a dielectric diffusion barrier not shown; [0072]) from the first substrate (202).
Re claim 6, Chang discloses the semiconductor device of claim 1, further comprising a second substrate (52; [0023]) bonded (by 56; [0023]) to a side (bottom) of the first insulating layer (IMD layers 214 of 210) facing away from (below) the first substrate (202).
Re claim 7, Chang discloses the semiconductor device of claim 1, wherein each of the first (of 210) and second (of 310) insulating layers (IMD layers 214/314) comprises a single layer ([0041] and [0049]) or a plurality of dielectric layers (as in IMD 114; [0028] and [0041] and [0049]).
Re claim 8, Chang discloses the semiconductor device of claim 1, wherein each of the first (of 210) and second (of 310) interconnect structures (metal features 216/316) comprises a plurality of conductive layers (metal features 216/316; [0041] and [0049]) stacked one above another (layered) and at least one conductive plug (unlabeled narrow features above/below metal features 216/316) connecting adjacent (immediately above/below) conductive layers (metal features 216/316).
Re claim 9, Chang discloses the semiconductor device of claim 8, wherein each conductive layer (metal features 216/316) of the first (of 210) and/or second (of 310) interconnect structures (metal features 216 of 210 and/or 316 of 310) is formed in a corresponding dielectric layer (an IMD layer 214/314) in the first insulating layer (IMD layers 214 of 210) and/or the second insulating layer (IMD layers 314 of 310).
Re claim 10, Chang discloses the semiconductor device of claim 6, wherein the second substrate (52) is bonded to the first substrate (202) through a bonding layer (56 and/or 40/230; [0023]; [0038] and [0040]) that is bonded to the first insulating layer (an IMD layer 214/314) or the second insulating layer (IMD layers 314 of 310).
Re claim 11, Chang discloses in FIGS. 3A-3I (with references to FIGS. 1A-1C) a method for making a semiconductor device, comprising:
providing a first substrate (202 in FIG. 3A; [0077]) having a front side (first side; [0041) and a backside (second side) opposite to the front side (first side), wherein a device structure (unlabeled integrated circuit region comprising gate electrodes 204 in FIG. 3A; [0042] and [0077]) is formed at the front side (first side) of the first substrate (202);
forming a first insulating layer (unlabeled IMD layers 214 of 210 in FIG. 3A; [0040]-[0041] and [0077]) on the front side (first side) of the first substrate (202);
forming a first interconnect structure (unlabeled metal features 216 of 210 in FIG. 3A; [0041]-[0042] and [0077) and a plug structure in the first insulating layer (unlabeled IMD layers 214 of 210), wherein the plug structure (unlabeled 250 in FIG. 3A; [0045] and [0077]) extends from the first insulating layer (unlabeled IMD layers 214 of 210) into the first substrate (202), and wherein a first end (bottom) of the plug structure (unlabeled 250) is electrically connected (for device interconnectivity and operation; [0042]; [0045] and [0077]) to the device structure (integrated circuit region comprising gate electrodes 204) through the first interconnect structure (metal features 216 of 210);
forming a deep trench capacitor (DTC 500 in FIG. 3H; [0086]) on the backside (second side) of the first substrate (202);
forming a second insulating layer (unlabeled IMD layers 314 of 310 in FIG. 3I; [0048]-[0049]; [0077] and [0087]) on the backside (second side) of the first substrate (202); and
forming a second interconnect structure (unlabeled metal features 316 of 310 in FIG. 3I; [0049]; [0077] and [0087]) in the second insulating layer (unlabeled IMD layers 314 of 310), wherein the second insulating layer (unlabeled IMD layers 314 of 310) covers (overlays) the DTC (500) and a second end (top) of the plug structure (unlabeled 250), and wherein the plug structure (unlabeled 250) is electrically connected (for device interconnectivity and operation; [0050] and [0074]-[0077]) at the second end (top side) to the DTC (500) through the second interconnect structure (metal features 316 of 310).
For the record, the examiner is interpreting the expression “electrically connected” to include direct and indirect connections between features for device operation.
Re claim 12, Chang discloses the method of claim 11, wherein the plug structure extends from the first insulating layer into the first substrate, and further extends through the first substrate (see claim 2).
Re claim 15, Chang discloses the method of claim 11, wherein forming the DTC (500) on the backside (second side) of the first substrate (202) comprises: forming a deep trench in the backside of the first substrate (see claim 4); forming a stack of at least two conductive material layers and at least one dielectric material layer located between adjacent conductive material layers (see claim 4), to form the DTC (500), wherein the at least two conductive material layers and the dielectric material layer further extend to the backside of the first substrate around the deep trench (see claim 4), and wherein the at least two conductive material layers are electrically isolated from the first substrate (see claim 4).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim 5; and 16 are rejected under 35 U.S.C. 103 as being unpatentable over Chang in view of KUO et al (US 2023/0352404 A1, hereafter Kuo).
Re claim 5, Chang discloses the semiconductor device of claim 4.
But, fails to disclose the semiconductor device further comprising: a first pad, a second pad and a third interconnect structure, each of the first and second pads formed on a side (top) of the second insulating layer (IMD layers 314 of 310) facing away from the first substrate (202), wherein the first pad is electrically connected to a portion of the at least two conductive material layers (502/504) in the DTC (500) and the second end (top) of the plug structure (250) through the second interconnect structure (metal features 316 of 310), wherein the third interconnect structure is formed in the second insulating layer (IMD layers 314 of 310), and wherein the second pad is electrically connected to a remaining portion of the at least two conductive material layers (502/504) in the DTC (500) through the third interconnect structure; and a passivation layer (312; [0048]) formed on the side (top) of the second insulating layer (IMD layers 314 of 310) facing away from (above) the first substrate (202), wherein the passivation layer (312) extends from the second insulating layer (IMD layers 314 of 310) and covers a portion of the first pad and a portion of the second pad.
However,
Kuo discloses in FIGS. 1 and 2B a semiconductor device (110; [0038]) comprising: a first pad (left 174; [0040]), a second pad (right 174; [0040]) and a third interconnect structure (right 130/140/…/170; [0040]), each of the first (left) and second (right) pads (174) formed on a side (top) of a second insulating layer (ILD layers 138/148/…/178 of 130/140/…/170; [0040]) facing away from a first substrate (110; [0026]), wherein the first pad (left 174) is electrically connected (through left 132/134; [0037]) to a portion (left side of 252) of at least two conductive material layers (252/256; [0037]) in a DTC (252/254/256; [0034]), wherein the third interconnect structure (right 130/140/…/170) is formed in the second insulating layer (ILD layers 138/148/…/178 of 130/140/…/170), and wherein the second pad (right 174) is electrically connected (through right 132/134; [0037]) to a remaining portion (middle of 256) of the at least two conductive material layers (252/256) in the DTC (252/254/256) through the third interconnect structure (right 130/140/…/170; [0040]).
Thus, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the structure of Chang with Kuo by first adding the first pad, the second pad and the third interconnect structure of Kuo, second using the DTC structure of Kuo for the DTC of Chang, such that each of the first and second pads formed on a side (top) of the second insulating layer (IMD layers 314 of 310) facing away from the first substrate (202), wherein the first pad is electrically connected to a portion of the at least two conductive material layers (502/504) in the DTC (500) and the second end (top) of the plug structure (250) through the second interconnect structure (metal features 316 of 310), wherein the third interconnect structure is formed in the second insulating layer (IMD layers 314 of 310), and wherein the second pad is electrically connected to a remaining portion of the at least two conductive material layers (502/504) in the DTC (500) through the third interconnect structure; and a passivation layer (312; [0048]) formed on the side (top) of the second insulating layer (IMD layers 314 of 310) facing away from (above) the first substrate (202), wherein the passivation layer (312) extends from the second insulating layer (IMD layers 314 of 310) and covers a portion of the first pad and a portion of the second pad, as an alternative way (rearrangement of parts, MPEP § 2144.04 VI. C.) to interconnect portions of the at least two conductive material layers (502/504) in the DTC (500) and the second end (top) of the plug structure (250) with other elements including the device structure of the semiconductor device.
Re claim 16, Chang and Kuo disclose the method of claim 15, wherein the method further comprises: forming a first pad and a second pad on a side of the second insulating layer facing away from the first substrate, wherein the first pad is electrically connected to a portion of the at least two conductive material layers in the DTC and the second end of the plug structure through the second interconnect structure, and wherein the second pad is electrically connected to a remaining portion of the at least two conductive material layers in the DTC through the third interconnect structure; and forming a passivation layer on the side of the second insulating layer facing away from the first substrate, wherein the passivation layer extends from the second insulating layer and covers a portion of the first pad and a portion of the second pad (see claim 5).
With respect to the limitations of wherein during the formation of the second interconnect structure in the second insulating layer, a third interconnect structure is further formed in the second insulating layer, the limitations would be rendered by Chang and Kuo since the second interconnect structure and the third interconnect structure would be formed in same layers in the second insulating layer.
Claim 13-14 and 17 are rejected under 35 U.S.C. 103 as being unpatentable over Chang in view of Zhu et al (US 2011/0227158 A1, hereafter Zhu).
Re claim 13, Chang discloses the method of claim 11, wherein an end surface (bottom) of the plug structure (250) located within the first insulating layer (IMD layers 214 of 210) is in a same layer as (co-planar with) any one of conductive layers (metal features 216 adjacent 250) in the first interconnect structure (metal features 216 of 210).
But fails to disclose, wherein in a process of forming the first interconnect structure (metal features 216 of 210) in the first insulating layer (IMD layers 214 of 210), during a formation of any conductive layer in the first interconnect structure (metal features 216 of 210), a hole is formed in the first insulating layer (IMD layers 214 of 210), and a conductive material is filled into the hole to form the plug structure (250).
However,
Zhu discloses in FIGS. 1a-1e a method for making a semiconductor device, comprising: wherein in a process of forming the first interconnect structure (16/24/26/28 in FIG. 1e; [0022] and [0025]) in a first insulating layer (12; [0022]), during a formation of any conductive layer (24 in FIG. 1c) in the first interconnect structure (16/24/26/28), a hole (17; [0023]) is formed in the first insulating layer (12), and a conductive material (22; is filled into the hole (17) to form a plug structure (TSV 22; [0024]).
Thus, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the method of Chang with Zhu by using a process of forming the first interconnect structure in the first insulating layer, during a formation of any conductive layer in the first interconnect structure, a hole is formed in the first insulating layer, and a conductive material is filled into the hole to form the plug structure, as disclosed by Zhu, so as to form a 3D integrated circuit, supply power to the formed 3D integrated circuit, or perform input/output (I/O) of the external signals (Zhu; [0026]).
Re claim 14, Chang discloses the method of claim 11, further comprising, before the DTC (500) is formed on the backside (second side) of the first substrate (202), bonding (by 56; [0023]) the first insulating layer (IMD layers 214 of 210) to a second substrate (52; [0023]).
But, fails to disclose and partially removing the first substrate (202) from the backside (second side) thereof so that the second end (top) of the plug structure (unlabeled 250) is exposed.
However, Zhu would render these limitations obvious by disclosing partially removing (grinding or thinning in FIG. 1e; [0027]) a first substrate (2; [0019]) from a backside (second side) thereof so that a second end (top) of the plug structure (TSV 22) is exposed ([0027]), as would be part of 3D IC discussed for claim 13.
Re claim 17, Chang discloses the method of claim 14, wherein bonding the first insulating layer to the second substrate comprises bonding the first insulating layer or the second insulating layer to a bonding layer (see claim 10).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ERIC W JONES whose telephone number is (408) 918-9765. The examiner can normally be reached M-F 7:00 AM - 6:00 PM PT.
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/ERIC W JONES/Primary Examiner, Art Unit 2892
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