DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Response to Arguments
Applicant's arguments filed on 08/05/2024 have been fully considered but they are not persuasive for at least the following reasons:
Applicant arguments:
Applicants respectfully submit that Bonilla fails to teach metal lines having different depths. Portions 152 and 154 in FIG. 1(b) of Bonilla cited by the Examiner clearly show the same depth for both portions. The Examiner disagrees.
In response:
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Bonilla discloses a copper interconnect line 150 having both regions 152 of polycrystalline grain structure and regions 154 of single crystal or bamboo grain structure (Para [ 0019]). At least some portion of region 152/154, having different depth, and d1 less than d2, based on the different grain shape, Para [ 0019]).
Examiner like to note that, claims recite a first metal line in the dielectric layer; a second metal line disposed in the dielectric layer; the dielectric layer comprising a first region without a via and a second region without a via. Since there is no via present in the dielectric layer, examiner interpreted based on the crystalline grain shape, at least some portion has different depth.
Thus, the well-made rejection included in the 04/30/2025 Non-Final Office Action is proper and hereby made FINAL.
Claim Rejection- 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 21, 26-28, 30-31, 33 and 37 are rejected under 35 U.S.C. 103 as being unpatentable over Baker-O’Neal et al (US 2009/0206484 A1; hereafter Baker) in view of Bonilla et al (US 2011/0175226 A1; hereafter Bonilla).
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Regarding claim 21. Baker discloses an integrated circuit comprising:
a substrate (Fig 6[c], substrate [not shown], Para [ 0069]) comprising a dielectric layer (dielectric layer 10, Para [ 0069]);
a first metal line (Fig 6[c], right side region 90, Para [ 0081]) comprising a narrow-line bamboo microstructure (Fig 6[c], right side region 90, Para [ 0081]) disposed in the dielectric layer (dielectric layer 10, Para [ 0069]);
a second metal line (Fig 6[c], left side region 90, Para [ 0081]) comprising microstructure disposed in the dielectric layer (dielectric layer 10, Para [ 0069]);
the dielectric layer (dielectric layer 10, Para [ 0069]) comprising a first region without a via (right side dielectric layer 10, Para [ 0069]) and a second region without a via (left side dielectric layer 10, Para [ 0069]);
But Baker does not disclose explicitly a second metal line comprising a narrow-line polycrystalline and wherein the first region comprises a portion of the first metal line having a depth dl; wherein the second region comprises a portion of the second metal line having a depth d2; and wherein dl is less than d2.
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In a similar field of endeavor, Bonilla discloses a second metal line comprising a narrow-line polycrystalline (Fig 1[b], region 152, Para [ 0019,0026]) and wherein the first region comprises a portion of the first metal line having a depth dl (Fig 1[b], region 154, Para [ 0019,0026]); wherein the second region comprises a portion of the second metal line having a depth d2 (Fig 1[b], region 152, Para [ 0019,0026]); and wherein dl is less than d2 (Fig 1[b], at least some portion of region 152/154, having different depth, and d1 less than d2, Para [ 0019,0026]).
Since Baker and Bonilla are both from the similar field of endeavor, and discloses copper interconnection line. Therefore, the purpose disclosed by Bonilla would have been recognized in the pertinent art of Baker. Therefore it would have been obvious to one of the ordinary skilled in the art before the effective filing date of the invention to combine Baker in light of Bonilla teaching “second metal line comprising a narrow-line polycrystalline (Fig 1[b], region 152, Para [ 0019,0026]) and wherein the first region comprises a portion of the first metal line having a depth dl (Fig 1[b], region 154, Para [ 0019,0026]); wherein the second region comprises a portion of the second metal line having a depth d2 (Fig 1[b], region 152, Para [ 0019,0026]); and wherein dl is less than d2 (Fig 1[b], at least some portion of region 152/154, having different depth, and d1 less than d2, Para [ 0019,0026])” for further advantage such as improved electromigration resistance characteristics.
Regarding claim 26. Baker and Bonilla disclose the integrated circuit of claim 22, Bonilla further disclose wherein the second metal line further comprises a narrow-line bamboo microstructure (Fig 1[b], region 152/154, Para [ 0019,0026]).
Therefore, it would have been obvious to one of the ordinary skilled in the art before the effective filing date of the invention to combine Baker in light of Bonilla teaching “wherein the second metal line further comprises a narrow-line bamboo microstructure (Fig 1[b], region 152/154, Para [ 0019,0026])” for further advantage such as improved electromigration resistance characteristics
Regarding claim 27. Baker and Bonilla disclose the integrated circuit of claim 21, Bonilla further disclose wherein the second metal line further comprises a narrow-line bamboo microstructure (Fig 1[b], region 152/154, Para [ 0019,0026]).
Therefore, it would have been obvious to one of the ordinary skilled in the art before the effective filing date of the invention to combine Baker in light of Bonilla teaching “wherein the second metal line further comprises a narrow-line bamboo microstructure (Fig 1[b], region 152/154, Para [ 0019,0026])” for further advantage such as improved electromigration resistance characteristics
Regarding claim 28. Baker and Bonilla disclose the integrated circuit of claim 21, Bonilla further disclose wherein the first metal line substantially comprises the narrow-line bamboo microstructure (Fig 1[b], region 152/154, Para [ 0019,0026]).
Therefore, it would have been obvious to one of the ordinary skilled in the art before the effective filing date of the invention to combine Baker in light of Bonilla teaching “wherein the first metal line substantially comprises the narrow-line bamboo microstructure (Fig 1[b], region 152/154, Para [ 0019,0026])” for further advantage such as improved electromigration resistance characteristics.
Regarding claim 30. Baker and Bonilla disclose the integrated circuit of claim 21, Baker further disclose wherein the dielectric layer comprises silicon, carbon, and oxygen (Para [ 0069]).
Regarding claim 31. Baker and Bonilla disclose the integrated circuit of claim 21, Baker further disclose wherein the dielectric layer comprises silicon, carbon, oxygen, and hydrogen (Para [ 0069]).
Regarding claim 33. Baker discloses an integrated circuit comprising:
a substrate (Fig 6[c], substrate [not shown], Para [ 0069]) comprising a dielectric layer (dielectric layer 10, Para [ 0069]);
a first metal line (Fig 6[c], right side region 90, Para [ 0081]) extending parallel to the substrate (Fig 6[c], substrate [not shown], Para [ 0069]) and comprising a narrow-line bamboo microstructure (Fig 6[c], right side region 90, Para [ 0081]), disposed in the dielectric layer (dielectric layer 10, Para [ 0069]);
a second metal line (Fig 6[c], left side region 90, Para [ 0081]) extending parallel to the substrate (Fig 6[c], substrate [not shown], Para [ 0069]) and comprising microstructure, disposed in the dielectric layer (dielectric layer 10, Para [ 0069]);
But Baker does not disclose explicitly a second metal line comprising a narrow-line polycrystalline and the first metal line having a depth dl, the second metal line having a depth d2, wherein dl is less than d2; and wherein dl and d2 are measured at locations away from any via connected to the first metal line and the second metal line respectively.
In a similar field of endeavor, Bonilla discloses a second metal line comprising a narrow-line polycrystalline (Fig 1[b], region 152, Para [ 0019,0026]) and the first metal line having a depth dl (Fig 1[b], region 154, Para [ 0019,0026]), the second metal line having a depth d2 (Fig 1[b], region 152, Para [ 0019,0026]); and wherein dl is less than d2 (Fig 1[b], at least some portion of region 152/154, having different depth, and d1 less than d2, Para [ 0019,0026]) and wherein dl and d2 are measured at locations away from any via connected to the first metal line and the second metal line respectively (Fig 1[b], at least some portion of region 152/154, having different depth, and d1 less than d2, Para [ 0019,0026]) .
Since Baker and Bonilla are both from the similar field of endeavor, and discloses copper interconnection line. Therefore, the purpose disclosed by Bonilla would have been recognized in the pertinent art of Baker. Therefore it would have been obvious to one of the ordinary skilled in the art before the effective filing date of the invention to combine Baker in light of Bonilla teaching “a second metal line comprising a narrow-line polycrystalline (Fig 1[b], region 152, Para [ 0019,0026]) and the first metal line having a depth dl (Fig 1[b], region 154, Para [ 0019,0026]), the second metal line having a depth d2 (Fig 1[b], region 152, Para [ 0019,0026]); and wherein dl is less than d2 (Fig 1[b], at least some portion of region 152/154, having different depth, and d1 less than d2, Para [ 0019,0026]) and wherein dl and d2 are measured at locations away from any via connected to the first metal line and the second metal line respectively (Fig 1[b], at least some portion of region 152/154, having different depth, and d1 less than d2, Para [ 0019,0026])” for further advantage such as improved electromigration resistance characteristics.
Regarding claim 37. Baker and Bonilla disclose the integrated circuit of claim 33, Baker further disclose wherein the first metal line substantially comprises the narrow-line bamboo microstructure (Fig 6[c], right side region 90, Para [ 0081]).
Claims 22- 25 and 34 are rejected under 35 U.S.C. 103 as being unpatentable over Baker-O’Neal et al (US 2009/0206484 A1; hereafter Baker) in view of Bonilla et al (US 2011/0175226 A1; hereafter Bonilla) as applied claims above and further in view of Yang et al (US 2009/0174075 A1; hereafter Yang).
Regarding claim 22. Baker and Bonilla disclose the integrated circuit of claim 21, But Baker and Bonilla do not disclose explicitly further comprising: a first liner disposed between the dielectric layer and the first metal line; a second liner disposed between the dielectric layer and the second metal line; and wherein the first liner and the second liner consist of the same material.
In a similar field of endeavor, Yang discloses a first liner (right barrier layer 14, Para [ 0022]) disposed between the dielectric layer (insulating layer 12, Para [ 0008]) and the first metal line (26b, Para [ 0008]);
a second liner (left barrier layer 14, Para [ 0022]) disposed between the dielectric layer (insulating layer 12, Para [ 0008]) and the second metal line; and wherein the first liner and the second liner consist of the same material (liner 14).
Therefore it would have been obvious to one of the ordinary skilled in the art before the effective filing date of the invention to combine Baker and Bonilla in light of Yang teaching “a first liner (right barrier layer 14, Para [ 0022]) disposed between the dielectric layer (insulating layer 12, Para [ 0008]) and the first metal line (26b, Para [ 0008]); a second liner (left barrier layer 14, Para [ 0022]) disposed between the dielectric layer (insulating layer 12, Para [ 0008]) and the second metal line; and wherein the first liner and the second liner consist of the same material (liner 14)” for further advantage such as better circuit performance with higher conductivity.
Regarding claim 23. Baker and Bonilla in light of Yang disclose the integrated circuit of claim 22, Yang further disclose wherein the first liner and the second liner comprise tantalum (Para [ 0022]).
Therefore, it would have been obvious to one of the ordinary skilled in the art before the effective filing date of the invention to combine Baker and Bonilla in light of Yang teaching “wherein the first liner and the second liner comprise tantalum (Para [ 0022])” for further advantage such as better circuit performance with higher conductivity. The applicant is reminded, in this regard, that it has been held that a mere selection of known materials generally understood to be suitable to make a device, the selection of the particular material being on the basis of suitability for the intended use, would be entirely obvious. See In re Leshin 227 F.2d 197, 125 USPQ 416 (CCPA 1960) and also Sinclair & Carroll Co. v. Interchemical Corp., 325 U.S. 327, 65 USPQ 297 (1945) (See. MPEP.2144.07).
Regarding claim 24. Baker and Bonilla in light of Yang disclose the integrated circuit of claim 22, But Baker and Yang do not disclose explicitly wherein the first liner and the second liner comprise cobalt.
In a similar field of endeavor, Bonilla discloses wherein the first liner and the second liner comprise cobalt (Para [ 0025]);
Therefore, it would have been obvious to one of the ordinary skilled in the art before the effective filing date of the invention to combine Baker and Yang in light of Bonilla teaching “wherein the first liner and the second liner comprise cobalt (Para [ 0025])” for further advantage such as better circuit performance with higher conductivity. The applicant is reminded, in this regard, that it has been held that a mere selection of known materials generally understood to be suitable to make a device, the selection of the particular material being on the basis of suitability for the intended use, would be entirely obvious. See In re Leshin 227 F.2d 197, 125 USPQ 416 (CCPA 1960) and also Sinclair & Carroll Co. v. Interchemical Corp., 325 U.S. 327, 65 USPQ 297 (1945). (See. MPEP.2144.07)
Regarding claim 25. Baker and Bonilla in light of Yang disclose the integrated circuit of claim 22, Yang further disclose wherein the first liner and the second liner comprise ruthenium (Para [ 0022]). The applicant is reminded, in this regard, that it has been held that a mere selection of known materials generally understood to be suitable to make a device, the selection of the particular material being on the basis of suitability for the intended use, would be entirely obvious. See In re Leshin 227 F.2d 197, 125 USPQ 416 (CCPA 1960) and also Sinclair & Carroll Co. v. Interchemical Corp., 325 U.S. 327, 65 USPQ 297 (1945). (See. MPEP.2144.07).
Therefore, it would have been obvious to one of the ordinary skilled in the art before the effective filing date of the invention to combine Baker and Bonilla in light of Yang teaching “wherein the first liner and the second liner comprise ruthenium (Para [ 0022])” for further advantage such as better circuit performance with higher conductivity.
Regarding claim 34. Baker and Bonilla disclose the integrated circuit of claim 33, But Baker and Bonilla do not disclose explicitly further comprising: a first liner disposed between the dielectric layer and the first metal line; a second liner disposed between the dielectric layer and the second metal line; and wherein the first liner and the second liner consist of the same material.
In a similar field of endeavor, Yang discloses a first liner (right barrier layer 14, Para [ 0022]) disposed between the dielectric layer (insulating layer 12, Para [ 0008]) and the first metal line (26b, Para [ 0008]);
a second liner (left barrier layer 14, Para [ 0022]) disposed between the dielectric layer (insulating layer 12, Para [ 0008]) and the second metal line; and wherein the first liner and the second liner consist of the same material (liner 14).
Therefore it would have been obvious to one of the ordinary skilled in the art before the effective filing date of the invention to combine Baker and Bonilla in light of Yang teaching “a first liner (right barrier layer 14, Para [ 0022]) disposed between the dielectric layer (insulating layer 12, Para [ 0008]) and the first metal line (26b, Para [ 0008]); a second liner (left barrier layer 14, Para [ 0022]) disposed between the dielectric layer (insulating layer 12, Para [ 0008]) and the second metal line; and wherein the first liner and the second liner consist of the same material (liner 14)” for further advantage such as better circuit performance with higher conductivity.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MOIN M RAHMAN whose telephone number is (571)272-5002. The examiner can normally be reached 8:30-5:00pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Julio Maldonado can be reached at 571-272-1864. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/MOIN M RAHMAN/Primary Examiner, Art Unit 2898
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