DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Claims 16-20 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected invention, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 07/08/2026.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 12 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. Claim 12 recites the limitation "shallow trench isolation" in line 2. There is insufficient antecedent basis for this limitation in the claim.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1, 7, 9, 13-15 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Shiliang et al. (U.S. Publication No. 2022/0102520 A1; hereinafter Shiliang)
With respect to claim 1, Shiliang discloses a semiconductor structure, wherein the semiconductor structure comprises: a first transistor, wherein the first transistor comprises: an epi [114]; a dielectric bar [112]; and a wrapped contact [125], wherein the wrapped contact has direct contact with three or more sides of the epi (see Figure 23).
With respect to claim 7, Shiliang discloses a second transistor, wherein the first transistor is an NFET and the second transistor is a PFET (see ¶[0022]).
With respect to claim 9, Shiliang discloses a system, wherein the system comprises: a semiconductor structure, wherein the semiconductor structure comprises: a first transistor, wherein the first transistor comprises: an epi [114]; stacked nanosheets [1012]; a dielectric bar [112/122], wherein the dielectric bar is directly connected to the stacked nanosheets (See Figure 19); and a wrapped contact [125], wherein the wrapped contact has direct contact with three or more sides of the epi (see Figure 25).
With respect to claim 13, Shiliang discloses a second transistor, wherein the second transistor is a same type as the first transistor, and wherein the second transistor comprises a second set of stacked nanosheets (See Figure 19; “type” is substantially broad as to be directed conductivity or physical type. As both are forksheet type transistors, they are the same type).
With respect to claim 14, Shiliang discloses wherein the dielectric bar is directly connected to the second set of stacked nanosheets (See Figure 19).
With respect to claim 15, Shiliang discloses wherein the second transistor further comprises a second epi [114], wherein: the epi and the second epi are separated by the dielectric bar and dielectric (See Figure 25).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 2-4 and 10-12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Shiliang in view of Xu et al. (U.S. Publication No. 2019/0214502 A1; hereinafter Xu).
With respect to claim 2, Shiliang fails to disclose wherein the direct contact with three or more sides of the epi comprises direct contact with a bottom side of the epi.
In the same field of endeavor, Xu teaches wherein the direct contact with three or more sides of the epi [132] comprises direct contact with a bottom side [156] of the epi (see Figure 16C). Implementation of an all around epi contact as taught by Xu reduces overall resistance of the source/drain region (see Xu ¶[0085]). Therefore, it would have been obvious to one of ordinary skill in the art at the time of invention that the combination of references would arrive at the claimed invention.
With respect to claim 3, the combination of Shiliang and Xu discloses wherein the direct contact with three or more sides of the epi further comprises direct contact with a top side and one or more sidewalls of the epi (see Shiliang Figure 23 and Xu Figure 16C).
With respect to claim 4, the combination of Shiliang and Xu discloses wherein a first width of a backside portion of the wrapped contact is greater than a second width of the epi (see Xu Figure 16C).
With respect to claim 10, Shiliang fails to disclose wherein the direct contact with three or more sides of the epi comprises direct contact with a bottom side of the epi. In the same field of endeavor, Xu teaches wherein the direct contact with three or more sides of the epi [132] comprises direct contact with a bottom side [156] of the epi (see Figure 16C). Implementation of an all around epi contact as taught by Xu reduces overall resistance of the source/drain region (see Xu ¶[0085]). Therefore, it would have been obvious to one of ordinary skill in the art at the time of invention that the combination of references would arrive at the claimed invention
With respect to claim 11, the combination of Shiliang and Xu discloses wherein the direct contact with three or more sides of the epi further comprises direct contact with a top side and one or more sidewalls of the epi (see Shiliang Figure 23 and Xu Figure 16C).
With respect to claim 12, the combination of Shiliang and Xu discloses wherein a first width between the dielectric bar and an end of the stacked nanosheets is less than a second width between the dielectric bar and shallow trench isolation (see Shiliang Figure 19).
Claim(s) 5 is/are rejected under 35 U.S.C. 103 as being unpatentable over Shiliang in view of Huang et al. (U.S. Publication No. 2021/0407999 A1; hereinafter Huang)
With respect to claim 5, Shiliang fails to disclose wherein a first height of the dielectric bar in a source/drain region of the semiconductor structure is less than a second height of the dielectric bar in a gate region of the semiconductor structure.
In the same field of endeavor, Huang teaches wherein a first height of the dielectric bar [201] in a source/drain region of the semiconductor structure is less than a second height of the dielectric bar [201] in a gate region of the semiconductor structure (See Figure 2). Increased height of dielectric bar allows for increased conductive isolation of each side of the gate structure (see Figure 2). Therefore, it would haven been obvious to one of ordinary skill in the art at the time of invention that the combination of references would arrive at the claimed invention.
Claim(s) 6 is/are rejected under 35 U.S.C. 103 as being unpatentable over Shiliang in view of Ryckaert et al. (U.S. Patent No. 12,324,175 B2; hereinafter Ryckaert)
With respect to claim 6, Shiliang discloses wherein: the first transistor further comprises stacked nanosheets [1012]; but fails to disclose a width between the dielectric bar and an end of the stacked nanosheets is a minimum of 6 nanometers and a maximum of 30 nanometers.
In the same field of endeavor, Ryckaert teaches a width between the dielectric bar [106] and an end of the stacked nanosheets is a minimum of 6 nanometers and a maximum of 30 nanometers (see Column 7, lines 50-55). Implementation of a proper width nanosheet, as taught by Ryckaert, allows for proper channel width and prevents resistivity (see Ryckaert Column 7, lines 50-55). Therefore, it would have been obvious to one of ordinary skill in the art at the time of invention that the combination of references would arrive at the claimed invention.
Claim(s) 8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Shiliang in view of Zhang et al. (U.S. Patent No. 11,289,484 B2; hereinafter Zhang)
With respect to claim 8, Shiliang fails to disclose wherein N2P space between the first transistor and the second transistor is a minimum of 25 nanometers and a maximum of 70 nanometers. In the same field of endeavor, Zhang teaches wherein N2P space between the first transistor and the second transistor is a minimum of 25 nanometers and a maximum of 70 nanometers (see Column 3, lines 62-67). It is well appreciated that the N2P spacing of around 50nm as taught by Zhang is the state of the art and allows for space reduction while minimizing crosstalk between transistors (see Zhang Column 3, lines 62-67). Therefore, it would have been obvious to one of ordinary skill in the art at the time of invention that the combination of references would arrive at the claimed invention.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. -- Xie et al. (U.S. Patent No. 9,847,390 B1) discloses a source/drain all around contact. - Sung et al. (U.S. Publication No. 2022/0093647 A1) discloses a forksheet transistor
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/JONATHAN HAN/Primary Examiner, Art Unit 2818
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