Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Claims 1-23 are presented for examination.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-3, 5-7, 10-12, 16-18 and 22-23 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Liu et al. (US Pub. No. 2020/0303644 A1), hereafter referred to as Liu.
As to claim 1, Liu discloses a semiconductor device (fig 1; [0018]) comprising:
a first electrode (fig 1, electrode 16);
a second electrode (24);
a variable resistance layer (20) positioned between the first electrode (16) and the second electrode (24) and maintaining a phase before and after a program operation ([0022];[0026]);
a non-conductive sealing layer (18) positioned between the first electrode (16) and the variable resistance layer (20); and
a nanostructure (17) positioned inside the non-conductive sealing layer (18) and spaced apart from the variable resistance layer (20).
As to claim 2, Liu discloses the semiconductor device of claim 1 (paragraphs above),
wherein the nanostructure (17) is electrically connected to the first electrode (16, [0022]).
As to claim 3, Liu discloses the semiconductor device of claim 1 (paragraphs above),
wherein the nanostructure includes nanodots contacting the first electrode ([0020] and [0022]).
As to claim 5, Liu discloses the semiconductor device of claim 1 (paragraphs above),
wherein the nanostructure has an electrical conductivity sufficient to function as a single integrated electrode together with the first electrode ([0022]).
As to claim 6, Liu discloses the semiconductor device of claim 5 (paragraphs above),
wherein the single integrated electrode has an effective area less than that of the second electrode (fig 1 and [0022]).
As to claim 7, Liu discloses the semiconductor device of claim 1 (paragraphs above),
wherein the non-conductive sealing layer is a diffusion barrier between the first electrode, the variable resistance layer, and the second electrode (fig 1, layer 18 provides a barrier to diffusion between 16, 20 and 22).
As to claim 10, Liu discloses the semiconductor device of claim 1 (paragraphs above),
wherein the variable resistance layer includes a chalcogenide material ([0020]).
As to claim 11, Liu discloses a semiconductor device (fig 1; [0018]) comprising:
a first electrode (16);
a second electrode (24);
a variable resistance layer (20) positioned between the first electrode (16) and the second electrode (24) and maintaining a phase before and after a program operation ([0022];[0026]);
a nanodot (17; [0020]) positioned on a surface of the first electrode (16); and
a non-conductive sealing layer (18) surrounding the nanodot (17) and filling between the first electrode (16) and the variable resistance layer (20) and between the nanodot (17) and the variable resistance layer (20).
As to claim 12, Liu discloses the semiconductor device of claim 11 (paragraphs above),
wherein the nanodot is electrically connected to the first electrode ([0022]), and has an electrical conductivity sufficient to function as a single integrated electrode together with the first electrode ([0022]).
As to claim 16, Liu discloses the semiconductor device of claim 11 (paragraphs above),
wherein the variable resistance layer includes a chalcogenide material ([0020]).
As to claim 17, Liu discloses a method of manufacturing a semiconductor device (figs 3-8; [0030]), the method comprising:
forming a first electrode (fig 3, 16);
forming a nanostructure on the first electrode (fig 4a, nanostructure 17 on electrode 16);
forming a non-conductive sealing layer (fig 6, 18) on the first electrode (16) to surround the nanostructure (17);
forming a variable resistance layer (20) on the non-conductive sealing layer (18); and
forming a second electrode (24) on the variable resistance layer (20).
As to claim 18, Liu discloses the method of claim 17 (paragraphs above),
wherein forming the nanostructure comprises forming a nanodot on a surface of the first electrode ([0020]).
As to claim 22, Liu discloses the method of claim 17 (paragraphs above),
wherein the variable resistance layer includes a chalcogenide material that maintains a phase before and after a program operation ([0020]).
As to claim 23, Liu discloses the method of claim 17 (paragraphs above),
applying a firing voltage to the first electrode and the second electrode ([0022], conditioning voltage is considered to be the firing voltage).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 4, 13 and 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Liu in view of Hua et al. (“A threshold switching selector based on highly ordered Ag nanodots for X-point memory applications”, Adv Science, 2019, 6, 1900024; provided with IDS received 12/18/2023), hereafter referred to as Hua.
As to claim 4, Liu discloses the semiconductor device of claim 1 (paragraphs above),
Liu does not disclose wherein the nanostructure includes at least one of nickel (Ni), silver (Ag), platinum (Pt), gold (Au), copper (Cu), and aluminum (Al).
Nonetheless, Hua discloses wherein the nanodots used in memory applications includes at least one of nickel (Ni), silver (Ag), platinum (Pt), gold (Au), copper (Cu), and aluminum (Al) (page 2, Ag nanodots shown in figure 1).
It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention to use silver for the nanodots of Liu as taught by Hua since this will provide a large localized electric field for the device switching.
As to claim 13, Liu discloses the semiconductor device of claim 11 (paragraphs above),
Liu does not disclose wherein the nanodot includes at least one of nickel (Ni), silver (Ag), platinum (Pt), gold (Au), copper (Cu), and aluminum (Al).
Nonetheless, Hua discloses wherein the nanodots used in memory applications includes at least one of nickel (Ni), silver (Ag), platinum (Pt), gold (Au), copper (Cu), and aluminum (Al) (page 2, Ag nanodots shown in figure 1).
It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention to use silver for the nanodots of Liu as taught by Hua since this will provide a large localized electric field for the device switching.
As to claim 19, Liu discloses the method of claim 17 (paragraphs above),
Liu does not disclose wherein the nanodot includes at least one of nickel (Ni), silver (Ag), platinum (Pt), gold (Au), copper (Cu), and aluminum (Al).
Nonetheless, Hua discloses wherein the nanodots used in memory applications includes at least one of nickel (Ni), silver (Ag), platinum (Pt), gold (Au), copper (Cu), and aluminum (Al) (page 2, Ag nanodots shown in figure 1).
It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention to use silver for the nanodots of Liu as taught by Hua since this will provide a large localized electric field for the device switching.
Allowable Subject Matter
Claims 8-9, 14-15 and 20-21 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: The prior art of record fails to teach or suggest wherein the non-conductive sealing layer has a thermal conductivity less than 20 W/mk, as recited in claims 8, 14 and 20; or wherein the non-conductive sealing layer includes at least one of FexOy, SiOx, TiOx, BNx, graphene, and SiNx, as recited in claims 9, 15 and 21.
Pertinent Art
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. US 2021/0151673A1; US2004/0149979A1.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SHAUN M CAMPBELL whose telephone number is (571)270-3830. The examiner can normally be reached on MWFS: 7:30-6pm Thurs 1-2pm.
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/SHAUN M CAMPBELL/Primary Examiner, Art Unit 2893 3/16/2026
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