DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Invention I in the reply filed on 4/15/2026 is acknowledged.
Claim 4 is withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected invention, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 4/15/2026.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-3 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Takeuchi et al. (US PG Pub 2015/0115286, hereinafter Takeuchi).
Regarding claim 1, figure 2 of Takeuchi discloses a diode comprising a semiconductor substrate (1) made of silicon carbide (¶ 41), the semiconductor substrate comprising:
a p-type first semiconductor region (3);
a drift region (2) in contact with a bottom portion of the first semiconductor region; and
an n-type second semiconductor region (1) in contact with a bottom portion of the drift region, wherein the drift region has a structure in which a plurality of p-type column regions and a plurality of n-type column regions are alternately arranged in a lateral direction,
the drift region includes a specific region (2a/5b) distributed over the plurality of p-type column regions and the plurality of n-type column regions in the lateral direction, at least at a part in a depth direction,
the plurality of p-type column regions has an effective p-type impurity concentration that is lower in the specific region (5b) than in a portion on a periphery of the specific region, and
the plurality of n-type column regions has an effective n-type impurity concentration that is higher in the specific region (2a) than in a portion on a periphery of the specific region.
Regarding claim 2, figure 2 of Takeuchi discloses the drift region (2) includes a plurality of the specific regions arranged at intervals in the depth direction.
Regarding claim 3, figure 2 of Takeuchi discloses a field effect transistor comprising:
a diode that includes a semiconductor substrate (1) made of silicon carbide (41), the semiconductor substrate including a p-type first semiconductor region (3), a drift region (4) in contact with a bottom portion of the first semiconductor region, and an n-type second semiconductor region (1) in contact with a bottom portion of the drift region;
a plurality of trenches (6) penetrating the first semiconductor region from an upper surface of the semiconductor substrate and reaching the n-type column region;
a gate insulating film (10) covering an inner surface of each of the plurality of trenches;
a gate electrode (9) disposed in each of the plurality of trenches and insulated from the semiconductor substrate by the gate insulating film, wherein in the diode,
the drift region has a structure in which a plurality of p-type column regions and a plurality of n-type column regions are alternately arranged in a lateral direction,
the drift region includes a specific region distributed over the plurality of p-type column regions and the plurality of n-type column regions in the lateral direction, at least at a part in a depth direction,
the plurality of p-type column regions has an effective p-type impurity concentration that is lower in the specific region (5b) than in a portion on a periphery of the specific region,
the plurality of n-type column regions has an effective n-type impurity concentration that is higher in the specific region (2a) than in a portion on a periphery of the specific region, and
the semiconductor substrate further includes an n-type source region (4) that is separated from the drift region by the first semiconductor region and is in contact with the gate insulating film.
Conclusion
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/YU-HSI D SUN/ Primary Examiner, Art Unit 2817
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