DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, and 3-11 are rejected under 35 U.S.C. 103 as being unpatentable over Wu et al. (US PG Pub 2025/0031403, hereinafter Wu) in view of Park et al. (US Pat 9,508,727, hereinafter Park).
Regarding claim 1, figures 1-20B of Wu disclose a semiconductor device, comprising:
at least one transistor comprising a gate structure (96, Fig. 15B) and a source/drain region (82, Fig. 15B);
a source/drain contact structure (120/122, Fig. 20B) disposed on the source/drain region, wherein the source/drain contact structure comprises a first metal layer (120) disposed in contact with the source/drain region and having a first thickness and second metal layer (122) disposed on the first metal layer and having a second thickness (measured vertically near the top of the tapered side portion) which is less than the first thickness, and wherein the second metal layer comprises a different material than the first metal layer (¶ 54).
Wu does not explicitly disclose a gate cut element disposed through a part of the gate structure, wherein the source/drain contact structure is disposed on a side of the gate cut element.
In the same field of endeavor, figure 2A of Park discloses a gate cut portion (IGR2) disposed through a part of a gate structure (GLA/GLB).
In light of such teachings, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to form a gate cut portion disposed through a part of the gate structure (and thus on a side of the source/drain contact structure), as taught by Park for the purpose of forming devices with reduced feature size while improving the stability and reliability (col. 1, lines 19-33).
Regarding claim 3, figures 18A-18B of Wu disclose a self-aligned contact cap layer (100) disposed on the gate structure (96), which runs across the entire length of the gate structure. Thus, it would be obvious that the gate cut element taught by Park is disposed through a part of the self-aligned contact cap layer.
Regarding claim 4, figures 18A-18B of Wu disclose a dielectric layer (102) disposed on the self-aligned contact cap layer (100), which runs across the entire length of the gate structure. Thus, it would be obvious that the gate cut element taught by Park is disposed through a part of the dielectric layer.
Regarding claim 5, figure 2A of Park discloses a top surface of the gate cut element (IGR2) is coplanar with a top surface of the overall gate structure including sidewall spacers (124). Thus in the combined invention, it would be obvious to have the top surface of the gate cut element be coplanar with the overall gate structure of Wu which includes the dielectric layer (102) and sidewall spacers (80),
Regarding claim 6, since a top surface of the gate cut element is coplanar with the overall gate structure which includes the dielectric layer (102) and sidewall spacers (80)(see claim 5 above), it would also be coplanar with a top surface of the second metal layer (122, see figure 20B of Wu).
Regarding claim 7, figures 1-20B of Wu disclose at least one additional transistor comprising an additional gate structure and an additional source/drain region (figure 20B shows multiple transistor structures);
The combined references as noted in the rejection of claim 1 would have an additional gate cut element disposed through a part of the additional gate structure. Furthermore, it is obvious to have an isolation region (ILD) between devices, which would be between the gate cut element and the additional gate cut element.
Regarding claim 8, the combined references as noted in the above rejections would include respective parts of the gate cut element and the additional gate cut element are disposed through the isolation region.
Regarding claim 9, figures 1-20B of Wu disclose an isolation region (56) that would be between the gate cut portion and the additional gate cut portion and also is disposed under a portion of the source/drain contact structure (120/122).
Regarding claim 10, figures 1-20B of Wu disclose an isolation region (56) that would be between the gate cut portion and the additional gate cut portion and comprises a shallow trench isolation region.
Regarding claim 11, Park discloses the gate cut element (IGR2) comprises a dielectric material (col. 24, lines 45-47).
Response to Arguments
Applicant’s arguments with respect to claim(s) 1 have been considered but are moot in light of the new grounds of rejection set forth above.
Allowable Subject Matter
Claims 12 and 14-20 are allowed.
Claim 2 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to YU-HSI DAVID SUN whose telephone number is (571)270-5773. The examiner can normally be reached Mon-Fri 8am-4pm ET.
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/YU-HSI D SUN/Primary Examiner, Art Unit 2817
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