DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of claims 11-16 and 18-20 in the reply filed on 4/6/26 is acknowledged.
Claim Objections
Claim 17 is missing.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 11-16 and 18-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over LIN et al. (US 2019/0229180, hereinafter, Lin) in view of Chatterjee (US 4,683,486.)
Regarding claims 11 and 20, in fig. 1 and 2C, Lin discloses an integrated circuit comprising:
a semiconductor layer 104a (para [0018] having a first surface;
trenches 111 extending from the first surface into the semiconductor layer (para [0024]);
a trench dielectric layer 110 lining a bottom and sidewalls of the trenches (para [0019]);
a doped polysilicon layer 112 within the trenches (para [0019]), the doped polysilicon layer further forming a polysilicon bridge that extends laterally over the first surface and connects to the doped polysilicon layer within the trenches; and
a contact region 180 (a circuit region and functions as a contact region, contact element 122c, for example) extending from the first surface into the semiconductor layer and laterally extending away from the polysilicon bridge.
Lin, as addressed above is a doped layer; however, Lin does not further disclose the bridge dopant concentration in the polysilicon bridge being greater than a trench dopant concentration in the trenches.
Chatterjee, in fig. 2, for example, discloses an analogous semiconductor device including a trench formed in a semiconductor substrate 34, a doped layer 20/48 formed on the trench and on the surface of the substrate. Chatterjee further shows the doped layer has a higher impurity concentration, P+ type on the top portion than the bottom portion in the trench, P-type in order to adjust the resistance and better contact in the regions. This is known in the art. The dopant concentration in this case may be adjusted during a routine of manufacturing to meet certain design purposes, resistance, for example.
Therefore, it would have been obvious to one of ordinary skill in the art at the time of the affective filing date would adjust the concentration as taught in order to take the advantage.
Regarding claim 12, the above combination further discloses the trenches are formed in an epitaxial layer over a handle substrate, the epitaxial layer having an epitaxial dopant concentration that is less than a substrate dopant concentration of the handle substrate (Lin’s para[0018] describes the layer has different doping levels.)
Regarding claims 13 and 14, the combination discloses the similar depths as claimed. See Lin’s fig. 1 and Chatterjee’s fig. 2.
Regarding claim 15, the combination discloses the trench dielectric layer includes a thermal oxide layer (para [0014].)
Regarding claim 16, Lin further discloses the thickness of the dielectric layer (para [0027]). The thickness of the layer in this case is considered to be a non-critical feature and the thickness can be adjusted during a routine of manufacturing.
Regarding claim 18, Lin discloses the trench dielectric includes an oxide-nitride-oxide layer (para [0027].).
Regarding claim 19, Lin shows an interconnect dielectric layer 121 over the first surface and over the polysilicon bridge;
a patterned metal layer 123 over the interconnect dielectric layer; and first and second conductive vias extending through the interconnect dielectric layer, the first conductive via conductively coupling a first section of the patterned metal layer to the substrate contact region and the second conductive via conductively coupling a second section of the patterned metal layer to the polysilicon bridge. Fig. 1.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to NATHAN W HA whose telephone number is (571)272-1707. The examiner can normally be reached M-T: 8:00AM-6:00PM.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, WAEL FAHMY can be reached at (571)-272-1705. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/NATHAN W HA/ Primary Examiner, Art Unit 2814
Prosecution Insights