DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Claims 16-20 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected invention, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 06/02/2026.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 1-15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Weckx et al (“Novel forksheet device architecture as ultimate logic scaling device towards 2nm”; hereinafter Weckx) in view of Lan et al. (U.S. Publication No. 2024/0021708 A1; hereinafter Lan).
With respect to claim 1, Weckx discloses a method for forming an integrated circuit device, comprising: forming a forksheet device on a frontside of a substrate (see Figure 5),
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the forksheet device comprising a first [p-gate] and a second transistor [n-gate] separated by a vertically oriented dielectric wall, wherein the forksheet device is formed over a base portion of the substrate and the dielectric wall extends into the base portion (See Figure 5); subsequent to forming the forksheet device, forming a first trench underneath the first transistor and a second trench underneath the second transistor the base portion from the backside, the first and second trenches being separated by the dielectric wall; and forming a first backside wiring line in the first trench and a second backside wiring line in the second trench (see Figure 5; 2 buried power rails). Weckx fails to disclose thinning the substrate from a backside of the substrate (see Figure 2P); subsequent to the thinning, forming a first trench underneath the first transistor and a second trench underneath the second transistor by etching the base portion from the backside.
In the same field of endeavor, Lan teaches thinning the substrate from a backside of the substrate; subsequent to the thinning, forming a trench underneath the transistors by etching the base portion from the backside (See Figure 2Q). Implementation of a backside etching as taught by Lan to produce the backside trenches of Weckz allows for ease of processing and allows for trench formations within acceptable ranges and improved conductive filling (See Lan ¶[0107] and ¶[0119]). Therefore, it would have been obvious to one of ordinary skill in the art at the time of invention
With respect to claim 2, the combination of Weckx and Lan discloses wherein the first and the second trenches are etched self-aligned to the dielectric wall [208] (see Lan Figure 2Q).
With respect to claim 3, the combination of Weckx and Lan discloses wherein the first and the second trenches are etched from a common opening patterned in a mask layer (see ¶[0035]).
With respect to claim 4, the combination of Weckx and Lan discloses wherein the base portion is a fin-shaped semiconductor portion protruding from the substrate (See Weckx Figure 5) and wherein the method comprises thinning the substrate from the backside to expose the base portion from the backside (see Lan Figure 2P).
With respect to claim 5, the combination of Weckx and Lan discloses wherein the base portion is a fin-shaped semiconductor portion protruding from the substrate (See Weckx Figure 5) and wherein the method comprises thinning the substrate from the backside to expose the base portion from the backside (see Lan Figure 2P).
With respect to claim 6, the combination of Weckx and Lan discloses wherein the base portion is a fin-shaped semiconductor portion protruding from the substrate (See Weckx Figure 5) and wherein the method comprises thinning the substrate from the backside to expose the base portion from the backside (see Lan Figure 2P).
With respect to claim 7, the combination of Weckx and Lan discloses wherein forming the first and second trenches comprises etching the base portion to remove the base portion along at least a part of a length dimension thereof (see Lan Figure 2Q).
With respect to claim 8, the combination of Weckx and Lan discloses wherein the dielectric wall is coextensive with a length dimension of the base portion (see Lan Figure 2Q).
With respect to claim 9, the combination of Weckx and Lan discloses wherein the base portion is surrounded by a shallow-trench isolation structure [214] (See Figure 2Q).
With respect to claim 10, the combination of Weckx and Lan discloses wherein the dielectric wall is coextensive with a length dimension of the base portion (see Lan Figure 2Q).
With respect to claim 11, the combination of Weckx and Lan discloses wherein the substrate comprises a first layer of a first semiconductor material and a second layer of a second semiconductor material on the first layer, wherein the second semiconductor material is different from each one of the first semiconductor material and a semiconductor material of the base portion (See Lan ¶[0012-0014]), wherein the base portion is formed on the second layer (See Weckx Figure 5 and Lan Figure 2O), and wherein thinning the substrate comprises removing the first layer from the backside using the second layer as a stop layer, and subsequently opening the second layer to expose the base portion (see Lan Figure 2O; ¶[0101]).
With respect to claim 12, the combination of Weckx and Lan discloses wherein the dielectric wall extends through the base portion to the second layer (See Figure 2Q).
With respect to claim 13, the combination of Weckx and Lan discloses wherein the substrate comprises a first layer of a first semiconductor material and a second layer of a second semiconductor material on the first layer, wherein the second semiconductor material is different from each one of the first semiconductor material and a semiconductor material of the base portion (See Lan ¶[0012-0014]), wherein the base portion is formed on the second layer (See Weckx Figure 5 and Lan Figure 2O), and wherein thinning the substrate comprises removing the first layer from the backside using the second layer as a stop layer, and subsequently opening the second layer to expose the base portion (see Lan Figure 2O; ¶[0101]).
With respect to claim 14, the combination of Weckx and Lan discloses wherein the first transistor and the second transistor are separated from the base portion by a bottom isolation layer [202], and wherein the method further comprises: patterning a via opening in the bottom isolation layer, the via opening exposing a source/drain region [138] of the first transistor; and forming a conductive via [246] in the via opening for connecting the first backside wiring line to the source/drain region (see Lan Figure 2T).
With respect to claim 15, the combination of Weckx and Lan discloses wherein a plurality of forksheet devices are formed along a length dimension of the base portion, each forksheet device comprising a first transistor and a second transistor separated by the dielectric wall, wherein the first trench and the first backside wiring line is formed underneath each first transistor and the second trench and the second backside wiring line is formed underneath each second transistor (See Weckx Figure 5 and 16; Lan Figure 2T).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. - Lilak et al. (U.S. Publication No. 2021/0296315 A1) discloses a forksheet transistor - Huang et al. (U.S. Publication No. 2021/0407999 A1) discloses a forksheet transistor
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JONATHAN HAN whose telephone number is (571)270-7546. The examiner can normally be reached 9.00-5.00PM PST.
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/JONATHAN HAN/Primary Examiner, Art Unit 2818
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