DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-10 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1 recites the limitation "the semiconductor layer" in line 3. There is insufficient antecedent basis for this limitation in the claim.
Note the dependent claims necessarily inherit the indefiniteness of the claims on which they depend.
Claim 1 would be allowable if rewritten or amended to overcome the rejection(s) under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph, set forth in this Office action.
Claims 2-10 would be allowable if rewritten to overcome the rejection(s) under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph, set forth in this Office action and to include all of the limitations of the base claim and any intervening claims.
Regarding claim 1, the closest prior art of record, Struble et al. (US PG Pub 2022/0321062), either singularly or in combination, does not disclose or suggest the combination of limitations including “An amplifier circuit comprising:
a first FET (Field Effect Transistor) including a first source electrode provided on the semiconductive layer and connected to a first reference potential in a high frequency manner, a first gate electrode provided on the semiconductive layer and inputting a high frequency signal, a first drain electrode provided on the semiconductive layer, and a first field plate having at least a part thereof provided above the semiconductive layer between the first gate electrode and the first drain electrode; and
a second FET including a second source provided on the semiconductive layer and electrically connected to the first drain, a second gate provided on the semiconductive layer and connected to a second reference potential in the high frequency manner, a second drain provided on the semiconductive layer and outputting a high frequency signal, and a second field plate having at least a part thereof provided above the semiconductor layer between the second gate electrode and the second drain electrode;
wherein a first distance between an end closer to the first drain electrode in ends of a surface of the first gate electrode facing the semiconductor layer and an end closer to the first drain electrode in ends of the first field plate is shorter than a second distance between an end closer to the second drain electrode in ends of a surface of the second gate electrode facing the semiconductor layer and an end closer to the second drain electrode in ends of the second field plate”.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to YU-HSI DAVID SUN whose telephone number is (571)270-5773. The examiner can normally be reached Mon-Fri 8am-4pm ET.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Marlon Fletcher can be reached at 571-272-2063. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/YU-HSI D SUN/ Primary Examiner, Art Unit 2817