Attorney Docket Number: 551216US Filing Date: 1 2 / 18 /2023 Claimed Foreign Priority Date: 12 / 20 /202 2 ( FR22 13950 ) Inventor s : Reboh et al. Examiner: Thomas McCoy DETAILED ACTION This Office action responds to the application filed 1 2 / 18 /2023. Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. In the event the determination of the status of the application as to AIA 35 U.S.C. 102 and 103 is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA) for a rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. Claim Objections Claim 2 is objected to because of the following informalities: Explicitly referring to the limitation as shown in the drawings (note the “…spacers (33)” text) is improper. Appropriate correction is required. Claim 4 is objected to because of the following informalities: “the spacers being formed facing said extension areas” cannot occur “before forming the spacers”, as is formatted within the claim. For the purpose of examination, the “the spacers being formed facing said extension areas” recitation will be construed to be recited outside the “before forming the spacers” preamble. Claim 7 is objected to because of the following informalities: “wherein after laser thermal annealing, regions based on metal material and semiconductor material compounds are formed…” is unclear. For the purpose of examination, the line will be construed to recite “wherein after laser thermal annealing , regions based on metal material and semiconductor material compounds are formed…” Claim Rejections - 35 USC § 112 The following is a quotation of 35 U.S.C. 112(b): (b ) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. The following is a quotation of 35 U.S.C. 112 (pre-AIA), second paragraph: The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the appl icant regards as his invention. Claim 1 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. Claim 1 recites the limitation "said gate block" in lines 4-5. There is insufficient antecedent basis for this limitation in the claim. For the purposes of examination, “said gate block” will be construed to recite “said transistor gate block”. Claim 1 also recites the limitation "said surface layer" in lines 3-4. There is insufficient antecedent basis for this limitation in the claim. For the purposes of examination, “the surface layer” will be construed to recite “the surface semiconductor layer”. Claim 1 also recites the limitation "said raised regions" in lines 11-12. There is insufficient antecedent basis for this limitation in the claim. For the purposes of examination, “said raised regions” will be construed to recite “said raised semiconductor regions”. Claim 1 also recites the limitation "said regions" in line 14. There is insufficient antecedent basis for this limitation in the claim. For the purposes of examination, “said regions” will be construed to recite “said raised semiconductor regions”. Claim 2 recites the limitation "the surface layer" in line 4. There is insufficient antecedent basis for this limitation in the claim. For the purposes of examination, “the surface layer” will be construed to recite “the surface semiconductor layer”. Claim 2 also recites the limitation "the spacers" in line 5. There is insufficient antecedent basis for this limitation in the claim. For the purposes of examination, “the spacers” will be construed to recite “the insulating spacers”. Claim 3 recites the limitation "the surface layer" in line 4. There is insufficient antecedent basis for this limitation in the claim. For the purposes of examination, “the surface layer” will be construed to recite “the surface semiconductor layer”. Claim 4 recites the limitation “the gate block" in lines 2-3 ,5 and 8 . There is insufficient antecedent basis for this limitation in the claim. For the purposes of examination, “the gate block” will be construed to recite “the transistor gate block”. Claim 4 also recites the limitation “spacers" in lines 2-4, 6, and 8. There is insufficient antecedent basis for this limitation in the claim. For the purposes of examination, “spacers” will be construed to recite “the insulating spacers”. Claim 5 recites the limitation “the gate block" in line 2. There is insufficient antecedent basis for this limitation in the claim. For the purposes of examination, “the gate block” will be construed to recite “the transistor gate block”. Claim 5 recites the limitation “the surface layer" in lines 3 -4 and 6. There is insufficient antecedent basis for this limitation in the claim. For the purposes of examination, “the surface layer ” will be construed to recite “the surface semiconductor layer ”. Claim 6 recites the limitation “these semiconductor regions" in line 3. There is insufficient antecedent basis for this limitation in the claim. For the purposes of examination, “these semiconductor regions” will be construed to recite “these raised semiconductor regions”. Claim 6 recites the limitation “ said surface layer" in line 5. There is insufficient antecedent basis for this limitation in the claim. For the purposes of examination, “ said surface layer” will be construed to recite “ said surface semiconductor layer”. Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis ( i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made . Claims 1 and 12 are rejected under 35 U.S.C. 103 as being unpatentable over Yu ( US 6403433 B 1 ) in view Reboh (US 20170345931 A1) further in view of Vellianitis (US 20200105527 A1) . Regarding claim 1, Yu (see, e.g., fig s. 2-4 ) shows most aspects of the instant invention including a method for producing a transistor comprising : Providing on a support ( e.g., thin film semiconductor layer 15 + insulative layer 17 ) provided with a surface semiconductor layer ( e.g., thin film semiconductor layer 15 ) and resting on an insulating layer ( e.g., insulative layer 17 ): at least one transistor gate block ( e.g., gate conductor 36 ) arranged on the surface semiconductor layer ( e.g., thin film semiconductor layer 15 ), insulating spacers ( e.g., spacers 32 ) surrounding said transistor gate block ( e.g., gate conductor 36 ), and raised semiconductor regions ( e.g., layer 53 + paragraph 13 “Layer 53 is preferably the same material as layer 15 (e.g., silicon)…” ) resting on the surface semiconductor layer ( e.g., thin film semiconductor layer 15 ) on either side of said transistor gate block ( e.g., gate conductor 36 ) and insulating spacers ( e.g., spacers 32 ); Making amorphous ( see, e.g., amorphization implant of fig. 14 ) the raised semiconductor regions ( e.g., layer 53 + paragraph 13 “Layer 53 is preferably the same material as layer 15 (e.g., silicon)…” ) and portions ( e.g., layer 15 portion vertically covered by layer 53 ) of the surface semiconductor layer ( e.g., thin film semiconductor layer 15 ) located under these raised semiconductor regions ( e.g., layer 53 + paragraph 13 “Layer 53 is preferably the same material as layer 15 (e.g., silicon)…” ) over the entire thickness of said raised semiconductor regions ( e.g., layer 53 + paragraph 13 “Layer 53 is preferably the same material as layer 15 (e.g., silicon)…” ) and said portions ( e.g., layer 15 portion vertically covered by layer 53 ) ; Doping ( see, e.g., paragraph 14 ) the raised semiconductor regions ( e.g., layer 53 + paragraph 13 “Layer 53 is preferably the same material as layer 15 (e.g., silicon)…” ) and said portions ( e.g., layer 15 portion vertically covered by layer 53 ); Yu (see, e.g., figs. 2-4), however, fails to show the amorphization process reaches the insulating layer, while it also fails to show carrying out at least one laser thermal annealing by means of one or more laser pulses so as to perform a recrystallisation of said raised regions and of said portions while carrying out an activation of dopants in said raised semiconductor regions and said portions. Reboh (see, e.g., paragraphs 65-66 ) , in a similar device to Yu, teaches laser annealing ( see, e.g., paragraph 66 “As a variant, this recrystallisation and this activation of dopants can be implemented by a laser to locally heat the semiconductor…” ) to perform recrystallisation ( see, e.g., paragraph 66 “As a variant, this recrystallisation … can be implemented by a laser to locally heat the semiconductor…” ) of raised semiconductor regions ( e.g., upper parts 128 and 130 ) and said portions ( e.g., lower parts 124 and 126 ) and activation of dopants ( see, e.g., paragraph 66 “As a variant, …this activation of dopants can be implemented by a laser to locally heat the semiconductor…” ) in said raised semiconductor regions ( e.g., upper parts 128 and 130 ) and said portions ( e.g., lower parts 124 and 126 ). Accordingly, it would have been obvious to one of ordinary skill in the art at the time of filing the invention to include the laser annealing for recrystallization and dopant activation of Reboh within the method of Yu, in order to provide improved material properties (recrystallisation) and ensuring the dopants become active within the device as desired, and laser annealing was a well-known technique at the time of filing the invention to utilize as a methodology for both of these steps, as taught by Reboh . Yu in view of Reboh , however, fails to teach the amorphous configuration reaches the insulating layer. Vellianitis (see, e.g., fig. 4), in a similar device to Yu in view of Reboh , teaches an entire amorphous semiconductor layer ( e.g., semiconductor layer 30 + paragraph 50 “…the semiconductor layer 30 is amorphous…” ), wherein the amorphous configuration reaches an insulating layer ( e.g., dielectric layer 20 ) . Accordingly, it would have been obvious to one of ordinary skill in the art at the time of filing the invention to include the fully amorphous configuration of Vellianitis within the semiconductor layer of Yu in view of Reboh , in order to achieve the expected result of providing a distinct and uniform amorphous configuration throughout the entire semiconductor layer region . Regarding claim 12, Yu (see, e.g., figs. 2-4) shows wherein the support ( e.g., thin film semiconductor layer 15 + insulative layer 17 ) is a substrate of semiconductor on insulator type such as a SOI substrate ( e.g., note that layer 15 + layer 17 is a silicon-on-insulator configuration (layer 15 is preferably silicon, see paragraph 3 of Yu) ). Claim s 2 -3 are rejected under 35 U.S.C. 103 as being unpatentable over Yu in view Reboh further in view of Vellianitis and Batude (US 20150044828 A1) . Regarding claim 2, Yu in view of Reboh further in view of Vellianitis fails to teach wherein the step of making amorphous said raised semiconductor regions and said portions is carried out by implantation using a beam inclined in relation to a normal to a main plane of the support, so as to produce an amorphization of areas of the surface semiconductor layer that extend under the insulating spacers. Batude (see, e.g., fig. 1A), in a similar device to Yu in view of Reboh further in view of Vellianitis , teaches an amorphous implantation beam inclined in relation to a normal to a main plane of a support ( see, e.g., paragraph 10 “…rendering amorphous … by means of one or more localized implantation(s)…” + paragraph 15 “Thus, at least one of said implantations at step a) may be carried out using a beam inclined with respect to a normal to the principal plane of the substrate…” ) so as to dope the areas of a surface semiconductor layer that extend under the spacers ( see, e.g., paragraph 15 “…such that said given regions of semi-conductor material rendered amorphous … extend under insulating spacers…” ). Accordingly, it would have been obvious to one of ordinary skill in the art at the time of filing the invention to include the inclined amorphous beam configuration of Batude in the method of Yu in view of Reboh further in view of Vellianitis , in order to provide an angled beam variation capable of reaching the semiconductor material under the insulating spacers during the amorphous implantation process. Regarding claim 3 , Yu in view of Reboh further in view of Vellianitis fails to teach wherein the step of doping said raised semiconductor regions and said portions comprises an implantation using a beam inclined in relation to a normal to a main plane of the support, so as to dope the areas of the surface semiconductor layer that extend under the insulating spacers. Batude (see, e.g., fig. 1A), in a similar device to Yu in view of Reboh further in view of Vellianitis , teaches a doping implantation beam inclined in relation to a normal to a main plane of the support ( see, e.g., paragraph 10 “…rendering … doping, by means of one or more localized implantation(s)…” + paragraph 15 “Thus, at least one of said implantations at step a) may be carried out using a beam inclined with respect to a normal to the principal plane of the substrate…” ) so as to dope the areas of the surface semiconductor layer that extend under the spacers ( see, e.g., paragraph 15 “…such that said given regions of semi-conductor material rendered … doped extend under insulating spacers…” ). Accordingly, it would have been obvious to one of ordinary skill in the art at the time of filing the invention to include the inclined amorphous beam configuration of Batude in the method of Yu in view of Reboh further in view of Vellianitis , in order to provide an angled beam variation capable of reaching the semiconductor material under the insulating spacers during the doping implantation process. Claims 4 -5 are rejected under 35 U.S.C. 103 as being unpatentable over Yu in view Reboh further in view of Vellianitis and Abou-Khalil (US 2012018 1 608 A1) . Regarding claim 4, Yu (see, e.g., figs. 2-4) shows forming the transistor gate block ( e.g., gate conductor 36 ) , forming the insulating spacers ( e.g., spacers 32 ) on either side of the transistor gate block ( e.g., gate conductor 36 ) , and forming said raised semiconductor regions ( e.g., layer 53 + paragraph 13 “Layer 53 is preferably the same material as layer 15 (e.g., silicon)…” ) on either side of the insulating spacers ( e.g., spacers 32 ), the insulating spacers ( e.g., spacers 32 ) being formed facing extension areas ( e.g., semiconductor regions of layer 15 underneath spacers 32 ) . Yu in view of Reboh further in view of Vellianitis , however, fails to teach after forming the transistor gate block and before forming the insulating spacers: doping so-called extension areas of the surface semiconductor layer located on either side of the transistor gate block. Abou-Khalil (see, e.g., fig s . 4 -5 ), in a similar device to Yu in view of Reboh further in view of Vellianitis , teaches doping ( e.g., angled ion-implantation 65 ) extension areas ( e.g., extension regions 60 ) of a surface semiconductor layer ( e.g., extension layer 45 ) located on either side of a transistor gate block ( e.g., gate body 50 ) before forming insulating spacers ( e.g., sidewall spacers 67 formed in fig. 5, after doping implantation process ). Accordingly, it would have been obvious to one of ordinary skill in the art at the time of filing the invention to use the doping implantation pre-spacer formation configuration of Abou-Khalil within the method of Yu in view of Reboh further in view of Vellianitis , in order to achieve the expected result of doping an entire layer during the fabrication process before blocking off specific areas of the semiconductor layer. Regarding claim 5, Yu in view of Reboh further in view of Vellianitis and Abou-Khalil teaches making amorphous and doping an upper part ( e.g., amorphous region 54, originating from semiconductor layer 15 ) of the semiconductor surface layer ( e.g., amorphous region 54 + layer 56, originating from layer 15 ) while keeping a crystalline lower layer ( e.g., layer 56 originating from semiconductor layer 15 + paragraph 15 “…thin region 56 remains as a crystalline material…” ) of the surface semiconductor layer ( e.g., amorphous region 54 + layer 56, originating from layer 15 ) carrying out annealing ( see, e.g., paragraph 66 of Reboh - “As a variant, this recrystallisation and this activation of dopants can be implemented by a laser to locally heat the semiconductor…” ) to perform recrystallisation ( see, e.g., paragraph 66 of Reboh - “As a variant, this recrystallisation … can be implemented by a laser to locally heat the semiconductor…” ) . While Yu in view of Reboh further in view of Vellianitis and Abou-Khalil doesn’t explicitly disclose th is annealing occurs during the extension area doping step, it would have been obvious to one of ordinary skill in the art at the time of filing the invention to combine the steps, in order to achieve the expected result of recrystallizing the upper portion of the surface semiconductor layer directly after the amorphous and dopant process. Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over Yu in view Reboh further in view of Vellianitis , Abou-Khalil, and Bacquie (US 20220270880 A1). Regarding claim 6, Yu (see, e.g., figs. 2-4) shows wherein after forming the insulating spacers ( e.g., spacers 32 ) and before amorphising ( e.g., amorphous implant of fig. 4 ) said raised semiconductor regions ( e.g., layer 53 + paragraph 13 “Layer 53 is preferably the same material as layer 15 (e.g., silicon)…” ) and said portions ( e.g., layer 15 portion vertically covered by layer 53 ) of the surface semiconductor layer ( e.g., thin film semiconductor layer 15 ) located under these raised semiconductor regions ( e.g., layer 53 + paragraph 13 “Layer 53 is preferably the same material as layer 15 (e.g., silicon)…” ) : forming the raised semiconductor regions ( e.g., layer 53 + paragraph 13 “Layer 53 is preferably the same material as layer 15 (e.g., silicon)…” ). Yu in view of Reboh further in view of Vellanitis and Abou-Khalil, however, fail to teach this forming of the raised semiconductor regions is done by epitaxy. Bacquie (see, e.g., paragraph 62), in a similar device to Yu in view of Reboh further in view of Vellianitis and Abou-Khalil, teaches forming raised semiconductor regions ( e.g., see, e.g., paragraph 62 “… raised source and drain zones from the active layer made of a semiconductor material …” ) by epitaxy ( see, e.g., paragraph 62 “…for example by epitaxy” ). Accordingly, it would have been obvious to one of ordinary skill in the art at the time of filing the invention to include the epitaxy methodology of Bacquie within the method of Yu in view of Reboh further in view of Vellianitis and Abou-Khalil, as epitaxy was a well-known technique at the time of filing the invention as a way to form raised semiconductor regions, as taught by Bacquie . In addition, note the recrystallisation of said upper parts of the surface semiconductor layer were already performed, so forming the raised regions would take place on said recrystallized upper parts. Claims 7- 8 are rejected under 35 U.S.C. 103 as being unpatentable over Yu in view Reboh further in view of Vellianitis and Nemouchi (US 20200161422 A1) . Regarding claim 7, Yu in view of Reboh further in view of Vellianitis fails to teach wherein after laser thermal annealing, regions based on metal material and semiconductor material compounds are formed in the raised semiconductor regions. Nemouchi (see, e.g., fig. 1D), in a similar device to Yu in view of Reboh further in view of Vellianitis teaches depositing ( see, e.g., paragraph 69 ) a metal material ( e.g., metal material 17 ) to cover a semiconductor material ( e.g., active area 4a ) so that after laser thermal annealing ( e.g., thermal annealing process of paragraph 72 ) , regions ( see, e.g., paragraph 75 ) based on metal material ( e.g., metal material 17 ) and semiconductor material ( e.g., active area 4a ) are formed. Accordingly, it would have been obvious to one of ordinary skill in the art at the time of filing the invention to include the metal-semiconductor interface and thermal annealing configuration of Nemouchi within the method of Yu in view of Reboh further in view of Vellianitis , in order to provide a silicide or similar material within the transistor setup (see, e.g., paragraphs 70 and 75 of Nemouchi ). Regarding claim 8, Nemouchi (see, e.g., fig. 1D), in a similar device to Yu in view of Reboh further in view of Vellianitis teaches before laser thermal annealing depositing ( e.g., thermal annealing process of paragraph 72 ), at least one metal material layer ( e.g., metal material 17 ) is deposited ( see, e.g., paragraph 69 ) so as to cover a semiconductor material ( e.g., active area 4a ), the laser thermal annealing ( e.g., thermal annealing process of paragraph 72 ) being adapted to form regions ( see, e.g., paragraph 75 ) based on metal material ( e.g., metal material 17 ) and semiconductor material ( e.g., active area 4a ). Accordingly, it would have been obvious to one of ordinary skill in the art at the time of filing the invention to include the metal-semiconductor interface and thermal annealing configuration of Nemouchi within the method of Yu in view of Reboh further in view of Vellianitis , in order to provide a silicide or similar material within the transistor setup (see, e.g., paragraph s 70 and 75 of Nemouchi ). Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Yu in view Reboh further in view of Vellianitis and Shimomura (US 20090181552 A1) . Regarding claim 10, Yu in view of Reboh further in view of Vellianitis fails to teach wherein the step of laser themal annealing is carried out using a laser by emitting one or more successive laser pulses, of pulse duration less than a microsecond and preferably between 1 ns and 1000 ns, advantageously between 20 ns and 300 ns, the laser having a wavelength between 200 nm and 600 nm and advantageously between 200 and 400 nm. Shimomura (see, e.g., fig. 14A), in a similar device to Yu in view of Reboh further in view of Vellianitis , teaches a laser pulse of preferably between 1 ns and 1000 ns, advantageously between 20 ns and 300 ns ( see, e.g., paragraph 114 “…a pulsed laser can be used…a pulse width of 2 5 nanoseconds…” ), the laser having a wavelength between 200 nm and 600 nm and advantageously between 200 and 400 nm ( see, e.g., paragraph 114 “ …and a wavelength of 308 nm can be used ” ) . Accordingly, it would have been obvious to one of ordinary skill in the art at the time of filing the invention to include the pulse duration and wavelength of Shimomura within the laser of Yu in view of Reboh further in view of Vellianitis , in order to provide precise duration/annealing control and a distinct wavelength profile as desired within the laser. Claim 11 is rejected under 35 U.S.C. 103 as being unpatentable over Yu in view Reboh further in view of Vellianitis and Wang (US 10644167 B2). Regarding claim 11, Reboh (see, e.g., paragraphs 65-66), in a similar device to Yu, teaches laser annealing ( see, e.g., paragraph 66 “As a variant, this recrystallisation and this activation of dopants can be implemented by a laser to locally heat the semiconductor…” ) to perform recrystallisation ( see, e.g., paragraph 66 “As a variant, this recrystallisation … can be implemented by a laser to locally heat the semiconductor…” ) of raised semiconductor regions ( e.g., upper parts 128 and 130 ) and said portions ( e.g., lower parts 124 and 126 ). Accordingly, it would have been obvious to one of ordinary skill in the art at the time of filing the invention to include the laser annealing for recrystallization and dopant activation of Reboh within the method of Yu in view of Reboh further in view of Vellianitis , in order to provide improved material properties (recrystallisation) within the device as desired, and laser annealing was a well-known technique at the time of filing the invention to utilize as a methodology for both of these steps, as taught by Reboh . In addition, see the claim rejection of claim 1, as the arguments are considered to be relevant here. Yu in view of Reboh further in view of Vellianitis , however, fails to teach wherein the raised semiconductor regions and said portions are transformed into polycrystalline material. Wang (see, e.g., figs. 1A-1F), in a similar device to Yu in view of Reboh further in view of Vellianitis , teaches a laser annealing process ( e.g., laser annealing of paragraph 15 ) transforms an amorphous silicon layer into polycrystalline material ( see, e.g., paragraph 15 “ The amorphous silicon film may then become a polysilicon film via laser crystallization or excimer laser annealing (ELA)…the amorphous silicon film may become the semiconductor layer 130 with polysilicon ” ) . 31. Accordingly, it would have been obvious to one of ordinary skill in the art at the time of filing the invention to include the polycrystalline material configuration of Wang in the method of Yu in view of Reboh further in view of Vellianitis , in order to increase the efficiency and durability of the semiconductor’s material profile. In addition, it should be noted that the configuration of Wang is substantially similar (laser annealing process on an amorphous silicon material) to that of Yu in view of Reboh further in view of Vellianitis , and the selection of a known material based on its suitability for its intended use supported a prima facie obviousness determination in Sinclair & Carroll Co. v. Interchemical Corp., 325 U.S. 327, 65 USPQ 297 (1945) (Claims to a printing ink comprising a solvent having the vapor pressure characteristics of butyl carbitol so that the ink would not dry at room temperature but would dry quickly upon heating were held invalid over a reference teaching a printing ink made with a different solvent that was nonvolatile at room temperature but highl y volatile when heated in view of an article which taught the desired boiling point and vapor pressure characteristics of a solvent for printing inks and a catalog teaching the boiling point and vapor pressure characteristics of butyl carbitol ) . Allowable Subject Matter Claim 9 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to Thomas McCoy at (571) 272-0282 and between the hours of 9:30 AM to 6:30 PM (Eastern Standard Time) Monday through Friday or by e-mail via Thomas.McCoy@uspto.gov. If attempts to reach the examiner by telephone are unsuccessful, the examiner's supervisor, Wael Fahmy, can be reached on (571) 272-1705. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /THOMAS WILSON MCCOY/ Examiner, Art Unit 2814 /WAEL M FAHMY/ Supervisory Patent Examiner, Art Unit 2814