Attorney Docket Number: 551216US
Filing Date: 12/18/2023
Claimed Foreign Priority Date: 12/20/2022 (FR22 13950)
Inventors: Reboh et al.
Examiner: Thomas McCoy
DETAILED ACTION
This Office action responds to the application filed 6/02/2026.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the
first inventor to file provisions of the AIA . In the event the determination of the status of the
application as to AIA 35 U.S.C. 102 and 103 is incorrect, any correction of the statutory basis
(i.e., changing from AIA to pre-AIA ) for a rejection will not be considered a new ground of
rejection if the prior art relied upon, and the rationale supporting the rejection, would be the
same under either status.
Acknowledgement
The Amendments filed on 6/02/2026, responding to the Office action mailed 3/27/2026, has been
entered. Applicant amended claims 1-14. The present Office action is made with all the suggested amendments being fully considered.
Response to Arguments
Applicant’s arguments, see page 11, filed 6/02/2026, with respect to the rejection of claim 1 under
35 U.S.C. 103 have been fully considered but are not found persuasive. The Applicant’s response filed 6/02/2026 argues that the Vellianitis fails to teach that layer 30 is fully amorphous, as the disclosure also presents polycrystalline as an alternative material. However, this simply means layer 30 could be amorphous OR polycrystalline, not expressly “partially amorphous and partially polycrystalline”. One of the embodiments is explicitly an amorphous layer, distinct from the alternative of a polycrystalline layer. The remarks regarding claims 13-14, however, have been considered and are fully persuasive. New grounds of rejection have been presented below in view of 35 U.S.C. 112 and 35 U.S.C. 103.
Claim Objections
Claim 13 is objected to because of the following informalities: the “…and extending over an entire thickness of the surface semiconductor layer…” is unclear. For the purposes of examination, the line will be construed to recite “…and the portions under the raised semiconductor regions also extend over an entire thickness of the surface semiconductor layer”. Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 7-11 and 14 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 7 recites the limitation "the laser thermal annealing" in line 3. There is insufficient antecedent basis for this limitation in the claim. For the purposes of examination, "the laser thermal annealing" will be construed to recite “the at least one laser thermal annealing”.
Claim 8 recites the limitation "the laser thermal annealing" in line 3. There is insufficient antecedent basis for this limitation in the claim. For the purposes of examination, "the laser thermal annealing" will be construed to recite “the at least one laser thermal annealing”.
Claim 9 recites the limitation "the laser thermal annealing" in line 2. There is insufficient antecedent basis for this limitation in the claim. For the purposes of examination, "the laser thermal annealing" will be construed to recite “the at least one laser thermal annealing”.
Claim 10 recites the limitation "the laser thermal annealing" in lines 1-2. There is insufficient antecedent basis for this limitation in the claim. For the purposes of examination, "the laser thermal annealing" will be construed to recite “the at least one laser thermal annealing”.
Claim 11 recites the limitation "the laser thermal annealing" in lines 1-2. There is insufficient antecedent basis for this limitation in the claim. For the purposes of examination, "the laser thermal annealing" will be construed to recite “the at least one laser thermal annealing”.
Claim 14 recites the limitation "the gate block" in line 5. There is insufficient antecedent basis for this limitation in the claim. For the purposes of examination, “the gate block” will be construed to recite “the at least one transistor gate block”.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1 and 12-14 are rejected under 35 U.S.C. 103 as being unpatentable over Yu (US 6403433 B1) in view Reboh (US 20170345931 A1) further in view of Vellianitis (US 20200105527 A1).
Regarding claim 1, Yu (see, e.g., figs. 2-4) shows most aspects of the instant invention including a method for producing a transistor comprising:
Providing on a structure on a support (e.g., thin film semiconductor layer 15 + insulative layer 17) provided with a surface semiconductor layer (e.g., thin film semiconductor layer 15) and resting on an insulating layer (e.g., insulative layer 17), the structure including at least one transistor gate block (e.g., gate conductor 36) arranged on the surface semiconductor layer (e.g., thin film semiconductor layer 15), insulating spacers (e.g., spacers 32) surrounding the at least one transistor gate block (e.g., gate conductor 36), and raised semiconductor regions (e.g., layer 53 + paragraph 13 “Layer 53 is preferably the same material as layer 15 (e.g., silicon)…”) resting on the surface semiconductor layer (e.g., thin film semiconductor layer 15) on either side of the at least one transistor gate block (e.g., gate conductor 36) and the insulating spacers (e.g., spacers 32);
Making amorphous (see, e.g., amorphization implant of fig. 14) the raised semiconductor regions (e.g., layer 53 + paragraph 13 “Layer 53 is preferably the same material as layer 15 (e.g., silicon)…”) and portions (e.g., layer 15 portion vertically covered by layer 53) of the surface semiconductor layer (e.g., thin film semiconductor layer 15) located under the raised semiconductor regions (e.g., layer 53 + paragraph 13 “Layer 53 is preferably the same material as layer 15 (e.g., silicon)…”) over an entire thickness of the raised semiconductor regions (e.g., layer 53 + paragraph 13 “Layer 53 is preferably the same material as layer 15 (e.g., silicon)…”) and said portions (e.g., layer 15 portion vertically covered by layer 53);
Doping (see, e.g., paragraph 14) the raised semiconductor regions (e.g., layer 53 + paragraph 13 “Layer 53 is preferably the same material as layer 15 (e.g., silicon)…”) and the portions (e.g., layer 15 portion vertically covered by layer 53);
Yu (see, e.g., figs. 2-4), however, fails to show the amorphization process reaches the insulating layer, while it also fails to show performing at least one laser thermal annealing using one or more laser pulses to recrystallize the raised semiconductor regions and the portions and to activate dopants therein.
Reboh (see, e.g., paragraphs 65-66), in a similar device to Yu, teaches laser annealing (see, e.g., paragraph 66 “As a variant, this recrystallisation and this activation of dopants can be implemented by a laser to locally heat the semiconductor…”) to recrystallize (see, e.g., paragraph 66 “As a variant, this recrystallisation … can be implemented by a laser to locally heat the semiconductor…”) the raised semiconductor regions (e.g., upper parts 128 and 130) and the portions (e.g., lower parts 124 and 126) and to active dopants therein (see, e.g., paragraph 66 “As a variant, …this activation of dopants can be implemented by a laser to locally heat the semiconductor…”).
Accordingly, it would have been obvious to one of ordinary skill in the art at the time of filing the invention to include the laser annealing for recrystallization and dopant activation of Reboh within the method of Yu, in order to provide improved material properties (recrystallisation) and ensuring the dopants become active within the device as desired, and laser annealing was a well-known technique at the time of filing the invention to utilize as a methodology for both of these steps, as taught by Reboh.
Yu in view of Reboh, however, fails to teach the amorphized portions extend to the insulating layer.
Vellianitis (see, e.g., fig. 4), in a similar device to Yu in view of Reboh, teaches an entire amorphous semiconductor layer (e.g., semiconductor layer 30 + paragraph 50 “…the semiconductor layer 30 is amorphous…”), wherein the amorphous semiconductor layer (e.g., semiconductor layer 30 + paragraph 50 “…the semiconductor layer 30 is amorphous…”) reaches an insulating layer (e.g., dielectric layer 20).
Accordingly, it would have been obvious to one of ordinary skill in the art at the time of filing the invention to include the fully amorphous configuration of Vellianitis within the semiconductor layer of Yu in view of Reboh, in order to achieve the expected result of providing a distinct and uniform amorphous configuration throughout the entire semiconductor layer region.
Regarding claim 12, Yu (see, e.g., figs. 2-4) shows wherein the support (e.g., thin film semiconductor layer 15 + insulative layer 17) includes a semiconductor-on-insulator substrate (e.g., note that layer 15 + layer 17 is a silicon-on-insulator configuration (layer 15 is preferably silicon, see paragraph 3)).
Regarding claim 13, Yu (see, e.g., fig. 3) shows the portions of the surface semiconductor layer (e.g., thin film semiconductor layer 15) located under the raised semiconductor regions (e.g., layer 53 + paragraph 13 “Layer 53 is preferably the same material as layer 15 (e.g., silicon)…”) correspond to regions of the surface semiconductor layer (e.g., thin film semiconductor layer 15) not covered not covered by the at least one transistor gate block (e.g., gate conductor 36) and the portions under the raised semiconductor regions (e.g., layer 53 + paragraph 13 “Layer 53 is preferably the same material as layer 15 (e.g., silicon)…”) also extend over an entire thickness of the surface semiconductor layer (e.g., thin film semiconductor layer 15).
Reboh (see, e.g., fig. 4) teaches amorphizing an entire surface (see, e.g., paragraph 62), including portions (e.g., second regions 116 + 118) of a surface semiconductor layer (e.g., first layer 104 + paragraph 57 “…of crystalline semiconductor”) under raised semiconductor regions (e.g., upper parts 128 + 130).
Accordingly, it would have been obvious to one of ordinary skill in the art at the time of filing the invention to include the uniform amorphizing configuration of Reboh within the amorphization process of Yu in view of Reboh further in view of Vellianitis, in order to achieve the expected result of enabling potential uniform doping across the wafer as desired, as opposed to providing a smaller profile for recrystallization during the manufacturing process. Also note since the amorphized region of the surface semiconductor layer now spans the entire thickness, the amorphized “portions” extend over the entire thickness of the surface semiconductor layer.
Regarding claim 14, Yu (see, e.g., figs. 2-6) shows making amorphous the raised semiconductor regions.
Reboh (see, e.g., fig. 4) teaches wherein making amorphous the raised semiconductor regions (e.g., upper parts 128 and 130) and the portions (e.g., lower parts 124 and 126) of the surface semiconductor layer (e.g., first portions 120, 122) is performed such that no crystalline seed remains (see, e.g., paragraph 62 “…these ion implantations destroy the crystalline structure of the lower parts 124.126 of the first portions 120, 122 and the second regions 116, 118 and make this semiconductor amorphous.”) within the surface semiconductor layer (e.g., first portions 120, 122).
Accordingly, it would have been obvious to one of ordinary skill in the art at the time of filing the invention to include the absolute amorphous implantation (i.e., heavy enough to lack a remaining crystalline seed below the surface semiconductor layer) of Reboh within the making amorphous of the surface semiconductor layer of Yu in view of Reboh further in view of Vellianitis, in order to achieve the expected result of enabling a larger profile for subsequent recrystallization within the device.
Claims 2-3 are rejected under 35 U.S.C. 103 as being unpatentable over Yu in view Reboh further in view of Vellianitis and Batude (US 20150044828 A1).
Regarding claim 2, Yu in view of Reboh further in view of Vellianitis fails to teach wherein making amorphous includes ion implantation using a beam inclined relative to a normal to a main plane of the support, such that portions of the surface semiconductor layer extending under the insulating spacers are amorphized.
Batude (see, e.g., fig. 1A), in a similar device to Yu in view of Reboh further in view of Vellianitis, teaches wherein making amorphous includes ion implantation using a beam inclined relative to a normal to a main plane of the support (see, e.g., paragraph 10 “…rendering amorphous…by means of one or more localized implantation(s)…” + paragraph 15 “Thus, at least one of said implantations at step a) may be carried out using a beam inclined with respect to a normal to the principal plane of the substrate…”), such that portions of a surface semiconductor layer extending under insulating spacers are amorphized (see, e.g., paragraph 15 “…such that said given regions of semi-conductor material rendered amorphous…extend under insulating spacers…”).
Accordingly, it would have been obvious to one of ordinary skill in the art at the time of filing the invention to include the inclined amorphous beam configuration of Batude in the method of Yu in view of Reboh further in view of Vellianitis, in order to provide an angled beam variation capable of reaching the semiconductor material under the insulating spacers during the amorphous implantation process, as well as preventing undesired ion channeling effects within the wafer during the implantation process.
Regarding claim 3, Yu in view of Reboh further in view of Vellianitis fails to teach wherein doping said raised semiconductor regions and the said portions includes implantation using a beam inclined relative to a normal to a main plane of the support, such that portions of the surface semiconductor layer extending under the insulating spacers are doped.
Batude (see, e.g., fig. 1A), in a similar device to Yu in view of Reboh further in view of Vellianitis, teaches doping said raised semiconductor regions and the said portions includes implantation using a beam inclined relative to a normal to a main plane of the support (see, e.g., paragraph 10 “…rendering…doping, by means of one or more localized implantation(s)…” + paragraph 15 “Thus, at least one of said implantations at step a) may be carried out using a beam inclined with respect to a normal to the principal plane of the substrate…”), such that portions of the surface semiconductor layer extending under the insulating spacers are doped (see, e.g., paragraph 15 “…such that said given regions of semi-conductor material rendered…doped extend under insulating spacers…”).
Accordingly, it would have been obvious to one of ordinary skill in the art at the time of filing the invention to include the inclined amorphous beam configuration of Batude in the method of Yu in view of Reboh further in view of Vellianitis, in order to provide an angled beam variation capable of reaching the semiconductor material under the insulating spacers during the doping implantation process.
Claims 4-5 are rejected under 35 U.S.C. 103 as being unpatentable over Yu in view Reboh further in view of Vellianitis and Abou-Khalil (US 20120181608 A1).
Regarding claim 4, Yu (see, e.g., figs. 2-4) shows forming the at least one transistor gate block (e.g., gate conductor 36), forming the insulating spacers (e.g., spacers 32) facing extension regions (e.g., semiconductor regions of layer 15 underneath spacers 32), and forming the raised semiconductor regions (e.g., layer 53 + paragraph 13 “Layer 53 is preferably the same material as layer 15 (e.g., silicon)…”) on opposite sides of the insulating spacers (e.g., spacers 32).
Yu in view of Reboh further in view of Vellianitis, however, fails to teach doping extension regions of a surface semiconductor layer on opposite sides of the at least one
Abou-Khalil (see, e.g., figs. 4-5), in a similar device to Yu in view of Reboh further in view of Vellianitis, teaches doping (e.g., angled ion-implantation 65) extension areas (e.g., extension regions 60) of a surface semiconductor layer (e.g., extension layer 45) on opposite sides of at least one transistor gate block (e.g., gate body 50).
Accordingly, it would have been obvious to one of ordinary skill in the art at the time of filing the invention to use the doping implantation pre-spacer formation configuration of Abou-Khalil within the method of Yu in view of Reboh further in view of Vellianitis, in order to achieve the expected result of doping an entire layer during the fabrication process before blocking off specific areas of the semiconductor layer.
Regarding claim 5, Yu in view of Reboh further in view of Vellianitis and Abou-Khalil teaches making amorphous and doping an upper portion (e.g., amorphous region 54, originating from semiconductor layer 15) of the surface semiconductor layer (e.g., amorphous region 54 + layer 56, originating from layer 15) while maintaining a crystalline lower layer (e.g., layer 56 originating from semiconductor layer 15 + paragraph 15 “…thin region 56 remains as a crystalline material…”) of the surface semiconductor layer (e.g., amorphous region 54 + layer 56, originating from layer 15), and annealing (see, e.g., paragraph 66 of Reboh - “As a variant, this recrystallisation and this activation of dopants can be implemented by a laser to locally heat the semiconductor…”) to recrystallize (see, e.g., paragraph 66 of Reboh - “As a variant, this recrystallisation … can be implemented by a laser to locally heat the semiconductor…”) the upper portion of the surface semiconductor layer (e.g., amorphous region 54 + layer 56, originating from layer 15).
While Yu in view of Reboh further in view of Vellianitis and Abou-Khalil doesn’t explicitly disclose this annealing occurs during the extension region doping step, it would have been obvious to one of ordinary skill in the art at the time of filing the invention to combine the steps, in order to achieve the expected result of recrystallizing the upper portion of the surface semiconductor layer directly after the amorphous and dopant process.
Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over Yu in view Reboh further in view of Vellianitis, Abou-Khalil, and Bacquie (US 20220270880 A1).
Regarding claim 6, Yu (see, e.g., figs. 2-4) shows wherein after forming the insulating spacers (e.g., spacers 32) and before making amorphous (e.g., amorphous implant of fig. 4), forming the raised semiconductor regions (e.g., layer 53 + paragraph 13 “Layer 53 is preferably the same material as layer 15 (e.g., silicon)…”) on the recrystallized upper portion (see, e.g., paragraph 15) of the surface semiconductor layer (e.g., thin film semiconductor layer 15 + region 54 extending from layer 15).
Yu in view of Reboh further in view of Vellanitis and Abou-Khalil, however, fails to explicitly teach this forming of the raised semiconductor regions is done by epitaxy.
Bacquie (see, e.g., paragraph 62), in a similar device to Yu in view of Reboh further in view of Vellianitis and Abou-Khalil, teaches forming raised semiconductor regions (e.g., see, e.g., paragraph 62 “…raised source and drain zones from the active layer made of a semiconductor material…”) by epitaxy (see, e.g., paragraph 62 “…for example by epitaxy”).
Accordingly, it would have been obvious to one of ordinary skill in the art at the time of filing the invention to include the epitaxy methodology of Bacquie within the method of Yu in view of Reboh further in view of Vellianitis and Abou-Khalil, as epitaxy was a well-known technique at the time of filing the invention as a way to form raised semiconductor regions, as taught by Bacquie. In addition, note the recrystallisation of said upper parts of the surface semiconductor layer were already performed, so forming the raised regions would take place on the recrystallized upper portions.
Claims 7-8 are rejected under 35 U.S.C. 103 as being unpatentable over Yu in view Reboh further in view of Vellianitis and Nemouchi (US 20200161422 A1).
Regarding claim 7, Yu in view of Reboh further in view of Vellianitis fails to teach forming regions including a metal-semiconductor compound in the raised semiconductor regions after the at least one laser thermal annealing.
Nemouchi (see, e.g., fig. 1D), in a similar device to Yu in view of Reboh further in view of Vellianitis teaches depositing (see, e.g., paragraph 69) a metal material (e.g., metal material 17) to cover a semiconductor material (e.g., active area 4a) so that after the at least one laser thermal annealing (e.g., thermal annealing process of paragraph 72), regions (see, e.g., paragraph 75) based on metal-semiconductor compound (e.g., metal material 17 + active area 4a) are formed.
Accordingly, it would have been obvious to one of ordinary skill in the art at the time of filing the invention to include the metal-semiconductor interface and thermal annealing configuration of Nemouchi within the method of Yu in view of Reboh further in view of Vellianitis, in order to provide a silicide or similar material within the transistor setup (see, e.g., paragraphs 70 and 75 of Nemouchi).
Regarding claim 8, Nemouchi (see, e.g., fig. 1D), in a similar device to Yu in view of Reboh further in view of Vellianitis, teaches depositing (e.g., thermal annealing process of paragraph 72) at least one metal material layer (e.g., metal material 17) so as to cover a semiconductor material (e.g., active area 4a), before the at least one laser thermal annealing (e.g., thermal annealing process of paragraph 72), wherein the at least one laser thermal annealing (e.g., thermal annealing process of paragraph 72) forms the metal-semiconductor compound (see, e.g., paragraph 75, also metal material 17 + active area 4a).
Accordingly, it would have been obvious to one of ordinary skill in the art at the time of filing the invention to include the metal-semiconductor interface and thermal annealing configuration of Nemouchi within the method of Yu in view of Reboh further in view of Vellianitis, in order to provide a silicide or similar material within the transistor setup (see, e.g., paragraphs 70 and 75 of Nemouchi).
Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Yu in view Reboh further in view of Vellianitis and Shimomura (US 20090181552 A1).
Regarding claim 10, Yu in view of Reboh further in view of Vellianitis fails to teach the at least one laser thermal annealing is performed using one or more laser pulses having a duration of less than 1 microsecond and a wavelength between 200 nm and 600 nm.
Shimomura (see, e.g., fig. 14A), in a similar device to Yu in view of Reboh further in view of Vellianitis, teaches one or more laser pulses having a duration of less than 1 microsecond (see, e.g., paragraph 114 “…a pulsed laser can be used…a pulse width of 25 nanoseconds…”) and a wavelength between 200 nm and 600 nm (see, e.g., paragraph 114 “…and a wavelength of 308 nm can be used”).
Accordingly, it would have been obvious to one of ordinary skill in the art at the time of filing the invention to include the pulse duration and wavelength of Shimomura within the at least one laser thermal annealing of Yu in view of Reboh further in view of Vellianitis, in order to provide precise duration/annealing control and a distinct wavelength profile as desired within the laser.
Claim 11 is rejected under 35 U.S.C. 103 as being unpatentable over Yu in view Reboh further in view of Vellianitis and Wang (US 10644167 B2).
Regarding claim 11, Reboh (see, e.g., paragraphs 65-66), in a similar device to Yu, teaches at least one laser thermal annealing (see, e.g., paragraph 66 “As a variant, this recrystallisation and this activation of dopants can be implemented by a laser to locally heat the semiconductor…”) recrystallizes (see, e.g., paragraph 66 “As a variant, this recrystallisation … can be implemented by a laser to locally heat the semiconductor…”) the raised semiconductor regions (e.g., upper parts 128 and 130) and the portions (e.g., lower parts 124 and 126).
Accordingly, it would have been obvious to one of ordinary skill in the art at the time of filing the invention to include the at least one laser annealing for recrystallization and dopant activation of Reboh within the method of Yu in view of Reboh further in view of Vellianitis, in order to provide improved material properties (recrystallisation) within the device as desired, and laser annealing was a well-known technique at the time of filing the invention to utilize as a methodology for both of these steps, as taught by Reboh. In addition, see the claim rejection of claim 1, as the arguments are considered to be relevant here.
Yu in view of Reboh further in view of Vellianitis, however, fails to teach wherein the raised semiconductor regions and said portions are transformed into polycrystalline material.
Wang (see, e.g., figs. 1A-1F), in a similar device to Yu in view of Reboh further in view of Vellianitis, teaches a laser annealing process (e.g., laser annealing of paragraph 15) transforms an amorphous silicon layer into polycrystalline material (see, e.g., paragraph 15 “The amorphous silicon film may then become a polysilicon film via laser crystallization or excimer laser annealing (ELA)…the amorphous silicon film may become the semiconductor layer 130 with polysilicon”).
Accordingly, it would have been obvious to one of ordinary skill in the art at the time of filing the invention to include the polycrystalline material configuration of Wang in the method of Yu in view of Reboh further in view of Vellianitis, in order to increase the efficiency and durability of the semiconductor’s material profile. In addition, it should be noted that the configuration of Wang is substantially similar (laser annealing process on an amorphous silicon material) to that of Yu in view of Reboh further in view of Vellianitis, and the selection of a known material based on its suitability for its intended use supported a prima facie obviousness determination in Sinclair & Carroll Co. v. Interchemical Corp., 325 U.S. 327, 65 USPQ 297 (1945) (Claims to a printing ink comprising a solvent having the vapor pressure characteristics of butyl carbitol so that the ink would not dry at room temperature but would dry quickly upon heating were held invalid over a reference teaching a printing ink made with a different solvent that was nonvolatile at room temperature but highly volatile when heated in view of an article which taught the desired boiling point and vapor pressure characteristics of a solvent for printing inks and a catalog teaching the boiling point and vapor pressure characteristics of butyl carbitol).
Allowable Subject Matter
Claim 9 would be allowable if rewritten to overcome the rejection(s) under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph, set forth in this Office action and to include all of the limitations of the base claim and any intervening claims.
Regarding claim 9, the primary art of record, Yu (US 6403433 B1) in view Reboh (US 20170345931 A1) further in view of Vellianitis (US 20200105527 A1) and Nemouchi (US 20200161422 A1) fails to teach after the laser thermal annealing; making amorphous upper portions of the raised semiconductor regions; depositing at least one metal material layer so as to cover the raised semiconductor regions, and annealing to form the metal-semiconductor compound in the upper portions. These features in combination with other elements in the claim are neither disclosed nor suggested by the prior art of record.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner
should be directed to Thomas McCoy at (571) 272-0282 and between the hours of 9:30 AM to 6:30 PM
(Eastern Standard Time) Monday through Friday or by e-mail via Thomas.McCoy@uspto.gov. If attempts
to reach the examiner by telephone are unsuccessful, the examiner's supervisor, Wael Fahmy, can be
reached on (571) 272-1705. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/THOMAS WILSON MCCOY/ Examiner, Art Unit 2814 /WAEL M FAHMY/Supervisory Patent Examiner, Art Unit 2814
Prosecution Insights