DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 7 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 7 recites the limitation "the substrate" in line 2. There is insufficient antecedent basis for this limitation in the claim.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-14 are rejected under 35 U.S.C. 103 as being unpatentable over CHUANG (US PG Pub 2022/0415784, hereinafter Chuang) in view of LALLEMAND et al. (US PG Pub 2024/0178183, hereinafter Lallemand).
Regarding claim 1, figure 19 of Chuang discloses a device comprising first (2) and second (1) chips, the first chip comprising an electronic circuit (¶ 20) and the second chip comprising a capacitor (C), the first and second chips being bonded to each other by molecular bonding (¶ 65), wherein the capacitor comprises a stack of a first insulating layer (16) between two second conductive layers (11, 17).
Chuang does not explicitly disclose the capacitor having a density greater than 700 nF/mm^2, and the stack being located in a first anodized metal region.
In the same field of endeavor, figure 4 of Lallemand disclose a capacitor of a density greater than 700 nF/mm^2 (¶ 4) with a stack (¶ 81) located in a first anodized metal region (¶ 66). (Figure 4 shows capacitor 110 within anodized region 104).
In light of such teachings, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to form the capacitor having a density greater than 700 nF/mm^2 with the stack being located in a first anodized metal region as taught by Lallemand for the purpose of forming a high capacitance device within a smaller space (¶ 3-4).
Furthermore, it would have been obvious to form the capacitor with a density within the claimed range, since it has been held by the Federal circuit that, where the only difference between the prior art and the claims was a recitation of relative dimensions of the claimed device and a device having the claimed relative dimensions would not perform differently than the prior art device, the claimed device was not patentably distinct from the prior art device. (In Gardner v. TEC Systems, Inc., 725 F.2d 1338, 220 USPQ 777 (Fed. Cir. 1984), cert. denied, 469 U.S. 830, 225 USPQ 232 (1984)).
Regarding claim 2, figure 19 of Chuang discloses the first chip (2) comprises an interconnection network and a semiconductor substrate inside and on top of which components of the electronic circuit are located (¶ 20).
Regarding claim 3, Chuang does not explicitly disclose the second chip (1) comprises a third insulating layer having a first planar surface and a second surface, the second surface being covered with a fourth layer comprising at least the first region.
However, multi-level metallizations with multiple insultating and conductive layers are well known in the art and it would have been obvious to form the claimed third insulating layer for the purpose of providing a fan-out structure to route signals to and from the device.
Regarding claim 4, figure 4 of Lallemand discloses the first region is surrounded with a fourth insulating anodized metal region (see various regions 104 in figure 4).
Regarding claim 5, figure 4 of Lallemand discloses the fourth layer of the second chip comprises second insulating anodized metal regions (104) and third metal regions (103), the third regions being separated by second regions.
Regarding claim 6, figure 19 of Chuang discloses the first (2) and second (1) chips are bonded by hybrid molecular bonding (¶ 3, 65).
Lallemand does not explicitly disclose the third insulating layer and the interconnection network comprising first conductive tracks located in contact with one another.
However, conductive tracks within multi-level metallizations (see claim 3 above) are well known in the art and it would have been obvious to form the claimed conductive tracks for the purpose of providing a fan-out structure to route signals to and from the device.
Regarding claim 7, figure 19 of Chuang discloses the surface of the substrate opposite to the interconnection network is covered with a fifth insulating layer (4) and second conductive tracks (22), the fifth layer and the second conductive tracks being configured to be bonded to the third layer and to the first tracks by molecular bonding (¶ 3, 65).
Regarding claim 8, figure 19 of Chuang discloses the device comprising vias (13, 14, 23, 24) extending in the first (2) and second (1) chips, crossing the third layer and reaching a conductive track buried in the interconnection network (see rejection of claims 3 and 5).
Chuang does not explicitly disclose the chips are bonded by oxide-to-oxide molecular bonding.
However, it would have been obvious to utilize oxide-to-oxide (well known in the art) molecular bonding for the purpose of choosing from a finite number of identified, predictable solutions, with a reasonable expectation of success (KSR International Co. v. Teleflex Inc. 82 USPQ2d 1385 (2007)).
Regarding claim 9, figure 4 of Lallemand discloses each of the terminals of the capacitor is coupled to a third region.
Regarding claim 10, figure 19 of Chuang discloses a method comprising forming a first chip (2) comprising an electronic circuit (¶ 20), and forming a second chip (1) comprising a capacitor (C), the method further comprising bonding of the first and second chips by molecular bonding (¶ 65), wherein the capacitor comprises a stack of a first insulating layer (16) between two second conductive layers (11, 17).
Chuang does not explicitly disclose the capacitor having a density greater than 700 nF/mm^2, and the stack being located in a first anodized metal region.
In the same field of endeavor, figure 4 of Lallemand disclose a capacitor of a density greater than 700 nF/mm^2 (¶ 4) with a stack (¶ 81) located in a first anodized metal region (¶ 66). (Figure 4 shows capacitor 110 within anodized region 104).
In light of such teachings, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to form the capacitor having a density greater than 700 nF/mm^2 with the stack being located in a first anodized metal region as taught by Lallemand for the purpose of forming a high capacitance device within a smaller space (¶ 3-4).
Furthermore, it would have been obvious to form the capacitor with a density within the claimed range, since it has been held by the Federal circuit that, where the only difference between the prior art and the claims was a recitation of relative dimensions of the claimed device and a device having the claimed relative dimensions would not perform differently than the prior art device, the claimed device was not patentably distinct from the prior art device. (In Gardner v. TEC Systems, Inc., 725 F.2d 1338, 220 USPQ 777 (Fed. Cir. 1984), cert. denied, 469 U.S. 830, 225 USPQ 232 (1984)).
Regarding claim 11, Chuang in view of Lallemand (figure 4) discloses the second chip comprises a third insulating layer having a first planar surface and a second surface, the second surface being covered with a fourth layer, comprising forming, on a support, of the third insulating layer and of an anodizable metal layer (103).
Regarding claim 12, Chuang in view of Lallemand (figure 4) discloses the fourth layer of the second chip comprises second insulating anodized metal regions (104) and third metal regions (103), the third regions being separated by second regions, comprising anodizing of the metal layer at the locations of the first and second regions.
Regarding claim 13, Chuang in view of Lallemand (figure 4) discloses the second chip comprises a third insulating layer having a first planar surface and a second surface, the second surface being covered with a fourth layer comprising at least the first region.
Chuang does not explicitly disclose bonding the first chip to a handle and removal of the support to expose the planar surface of the third layer.
However, use of and removal of a handle to bond wafers is well known in the art and it would have been obvious to utilize a handle in the bonding process for the purpose of choosing from a finite number of identified, predictable solutions, with a reasonable expectation of success (KSR International Co. v. Teleflex Inc. 82 USPQ2d 1385 (2007)).
Regarding claim 14, figure 19 of Chuang discloses the device comprising vias (13, 14, 23, 24) extending in the first (2) and second (1) chips, crossing the third layer and reaching a conductive track buried in the interconnection network (see rejection of claims 3 and 5).
Chuang does not explicitly disclose the chips are bonded by oxide-to-oxide molecular bonding.
However, it would have been obvious to utilize oxide-to-oxide (well known in the art) molecular bonding for the purpose of choosing from a finite number of identified, predictable solutions, with a reasonable expectation of success (KSR International Co. v. Teleflex Inc. 82 USPQ2d 1385 (2007)).
Conclusion
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/YU-HSI D SUN/Primary Examiner, Art Unit 2817
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