Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
OFFICE ACTION
This is a response to the application filed on
Claims 1-12 are pending.
Claim Objection
In claim 1, “mounded” should be replaced with “mounted”.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 6, 8 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
In claim 4, step (g) lacks antecedent basis because claim 4 depends on claim 3 and claim 3 depends on claim 1. Claims 1 and 3 do not recite two steps (e) and (f) to provide antecedent basis for step (g) in claim 4.
In claim 6, Step (g) lacks antecedent basis because claim 6 depends on claim 5 and claim 5 depends on claim 1. Claims 1 and 5 do not recite two steps ( e) and (f) to provide antecedent basis for step (g) in claim 6.
In claim 8, step (g) lacks antecedent basis because claim 8 depends on claim 7 and claim 7 depends on claim 1. Claims 1 and 7 do not recite two steps ( e) and (f) to provide antecedent basis for step (g) in claim 8
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) The claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) The claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-12 are rejected under 35 U.S.C. 102(a) (2) being anticipated by the prior art of record Yamakaji (US 2024/0280631)
Regarding claim 1, the prior art discloses:
A manufacturing method of an electronic device including a , substrate (see substrate/ printed circuit board in one or more of fig 1, 3, 6-10, 21-27, 33, 35) and a semiconductor device (IC 51 in one or more of fig 1, 3, 6-10, 21-27, 33, 35) mounded on the substrate, the manufacturing method comprising steps of:
(a) preparing a power supply model including impedance (see one or more of par 81, 96, 125, 150, 287 or one more of fig 18, 20, 40-42 ) information on a power supply path included in the electronic device (see one or more of par 81, 96, 125, 150, 287 or one more of fig 18, 20, 40-42);
(b) measuring a power supply noise on the substrate at time of operation of the electronic device (summary and/or one or more of fig 3, 18, 20-26, 42);
(c) calculating a power supply current inside the semiconductor device (see one or more of par 90, 95, 104, 110, 115, 125, 206-209, 246),) , based on the power supply noise and the power supply model; and
(d) simulating EMI characteristics (apply ac signal as noise, inject/apply noise /magnetic field ( abstract, par 5, 8, 81, 84, 88-95, 107-108, 127, 131, 143, 314, or fig 2, 28, 30, 34 and related text, simulating noise, electromagnetic field simulator (par 116, 353)), based on the power supply current and the power supply model.
(Claim 2) the step (a) includes steps of:(e) preparing a power supply model including impedance information on a power supply path inside the semiconductor device (see one or more of summary, par 199, 205-213, 222-225, 369-371 fig 2, 18, 20, 40-42); and (f) preparing a power supply model including impedance information on a power supply path on the substrate (see one or more of summary, par 199, 205-213, 222-225, 369-371 fig 2, 18, 20, 40-42).
(Claim 3) the steps (b), (c) and (d) are performed again (see iteration/loop process in fig 11, 16) after a design of the electronic device is changed based on a result of simulating the EMI characteristics at the step (d).
(Claim 4) a step of:(g) changing the design of the electronic device by changing a program (IC changed, rewritable software (par 114, 183)) to be written into the semiconductor device.
(Claim 5) the steps (a) and (d) are performed again (see iteration/loop process in fig 11, 16) after a design of the electronic device is changed based on a result of simulating the EMI characteristics at the step (d).
(Claim 6) a step of (g) changing the design of the electronic device by changing a layout of the semiconductor device.
(Claim 7) the steps (a), (b), (c) and (d) are performed again (see iteration process in fig 11, 16) after a design of the electronic device is changed based on a result of simulating the EMI characteristics at the step (d).
(Claim 8) a step of:(g) changing the design of the electronic device by changing a program to be written into the semiconductor device and a layout of the semiconductor device ((rewritable software, IC design are changed (Par 114, 183))
(Claim 9) at the step (b) of measuring the power supply noise, power supply noises of a plurality of power supplies are measured at the same phase (same frequency (par 199))
(Claim 10) at the step (c) of calculating the power supply current inside the semiconductor device, a transmission parameter (transmission line/characteristic, wiring transmitting signal, transmission antennas (fig 2, par 4-5, 77, 99, 244, 268, 353, 358)) is prepared based on the power supply model, and the power supply current inside the semiconductor device is calculated based on the transmission parameter (see one or more of fig 1-4, 12, 21-27, 35-39).
(Claim 11) the transmission parameter amplitude data and phase data on a frequency axis (see one or more of fig 12-17, 19, 31)
(Claim 12) at the step (c), a power supply voltage inside the semiconductor device is calculated based on the transmission parameter, and the power supply current inside the semiconductor device is calculated based on the power supply voltage inside the semiconductor device and the power supply model (see summary and/or one or more of fig 1, 3, 6-10, 21-27, 35-37 and related text)
Claims 1-2 and 9-12 are rejected under 35 U.S.C. 102(a) (1) being anticipated by the prior art of record Murai (US 2016/0157336)
Regarding claim 1, the prior art discloses:
A manufacturing method of an electronic device including a substrate (PCB in fig 1A) and a semiconductor device (semiconductor device 100/200 in fig 1A) mounded on the substrate, the manufacturing method comprising steps of:
(a) preparing a power supply model (abstract) including impedance information on a power supply path (see one or more par 92-97, 102, 113, 240, 264, 269, 319, 324) included in the electronic device;
(b) measuring a power supply noise on the substrate at time of operation of the electronic device (par 12, 89, 96, 116, 153-154, 187, 316);
(c) calculating a power supply current inside the semiconductor device, based on the power supply noise and the power supply model (see one or more of fig 1, 6, 9, 13, 15, 17, 20-23 and related text); and
(d) simulating EMI characteristics (impedance/ jitter/ electromagnetic simulation (par 108, 269, 291, 328)), based on the power supply current and the power supply model.
(Claim 2) the step (a) includes steps of:(e) preparing a power supply model including impedance information (see one or more par 92-97, 102, 113, 240, 264, 269, 319, 324) on a power supply path inside the semiconductor device; and (f) preparing a power supply model including impedance information on a power supply path on the substrate.
(Claim 9) at the step (b) of measuring the power supply noise, power supply noises of a plurality of power supplies are measured at the same phase (fig 16, 26).
(Claim 10) at the step (c) of calculating the power supply current inside the semiconductor device, a transmission parameter (see one or more of fig 1, 6, 9, 13, 15, 17, 20-23 and related text) is prepared based on the power supply model, and the power supply current inside the semiconductor device is calculated based on the transmission parameter (see one or more of fig 1, 6, 9, 13, 15, 17, 20-23 and related text)
(Claim 11) the transmission parameter includes amplitude data and phase data on a frequency axis (fig 16, 26)
(Claim 12) at the step (c), a power supply voltage inside the semiconductor device is calculated based on the transmission parameter, and the power supply current inside the semiconductor device is calculated based on the power supply voltage inside the semiconductor device and the power supply model (see one or more of fig 1, 6, 9, 13, 15, 17, 20-23 and related text)
Claims 1-8, 10-12 are rejected under 35 U.S.C. 102(a) (1) being anticipated by the prior art of record Ogawa (US 2013/0212551)
Regarding claim 1, the prior art discloses:
A manufacturing method of an electronic device including a substrate and a semiconductor device mounded on the substrate (fig 3), the manufacturing method comprising steps of:
(a) preparing a power supply model including impedance information on a power supply (see one or more of par 1-2, 14, 164, 180-182, 195, 198, 200, 215, 239, 249 ) path included in the electronic device;
(b) measuring a power supply noise (par 4-7, 106, 248) on the substrate at time of operation of the electronic device;
(c) calculating a power supply current inside the semiconductor device (see one or more of par 2, fig 14-19, 26-27, 36 and related text), based on the power supply noise and the power supply model; and
(d) simulating EMI characteristics (see simulator or SPICE and electromagnetic field in par 106, 147-248), based on the power supply current and the power supply model.
(Claim 2) the step (a) includes steps of:(e) preparing a power supply model including impedance (see one or more of par 1-2, 14, 164, 180-182, 195, 198, 200, 215, 239, 249 ) information on a power supply path inside the semiconductor device; and (f) preparing a power supply model including impedance information on a power supply path on the substrate (see one or more of par 1-2, 14, 164, 180-182, 195, 198, 200, 215, 239, 249 )
(Claim 3) the steps (b), (c) and (d) are performed again (see repeat process/operation/execution again in par 86, 93, 124-125, 357) after a design of the electronic device is changed based on a result of simulating the EMI characteristics at the step (d).
(Claim 4) a step of:(g) changing the design of the electronic device by changing a program to be written into the semiconductor device.
(Claim 5) the steps (a) and (d) are performed again (see repeat process/operation/execution again in par 86, 93, 124-125, 357) after a design of the electronic device is changed based on a result of simulating the EMI characteristics at the step (d).
(Claim 6) a step of (g) changing the design of the electronic device by changing a layout of the semiconductor device (abstract, par 13, 38-53, 290-294, 303, 316, 357).
(Claim 7) the steps (a), (b), (c) and (d) are performed again (see repeat process/operation/execution again in par 86, 93, 124-125, 357) after a design of the electronic device is changed based on a result of simulating the EMI characteristics at the step (d).
(Claim 8) a step of: (g) changing the design of the electronic device by changing a program to be written into the semiconductor device (par 281-284, 290-294, 301-303, 316, 326) and a layout of the semiconductor device (abstract, par 13, 38-53, 290-294, 301-303, 357).
(Claim 10) at the step (c) of calculating the power supply current inside the semiconductor device, a transmission parameter (fig 3, 6, 11, 19, 23, 26-27) is prepared based on the power supply model, and the power supply current inside the semiconductor device is calculated based on the transmission parameter.
(Claim 11) the transmission parameter includes amplitude data and phase data on a frequency axis (par 71, 82, 162, 164, 214-215, 240, 259-260).
(Claim 12) at the step (c), a power supply voltage inside the semiconductor device is calculated based on the transmission parameter (fig 3, 6, 11, 19, 23, 26-27), and the power supply current inside the semiconductor device is calculated based on the power supply voltage inside the semiconductor device and the power supply model (fig 3, 6, 11, 19, 23, 26-27)
Claims 1-3, 5, 7 and 9 are rejected under 35 U.S.C. 102(a) (1) being anticipated by the prior art of record Paoletti (US 2016/0157355)
Regarding claim 1, the prior art discloses:
A manufacturing method of an electronic device including a substrate (fig 3) and a semiconductor device (LSI 21 in fig 3) mounded on the substrate (fig 3), the manufacturing method comprising steps of:
(a) preparing a power supply model including impedance (see one or more of par 47-48, 60, 69, 101-102, 112, 114, 117) information on a power supply (abstract) path included in the electronic device;
(b) measuring a power supply noise on the substrate at time of operation of the electronic device (see one or more of abstract, field of invention, background, summary, fig 3-5, 8-9, 17);
(c) calculating a power supply current (abstract, background) inside the semiconductor device, based on the power supply noise and the power supply model; and
(d) simulating EMI characteristics (98 4, 25, 57, 80, 82, 87, 92), based on the power supply current and the power supply model.
(Claim 2) the step (a) includes steps of:(e) preparing a power supply model including impedance (par 47-48, 60, 69, 101-102, 112, 114, 117) information on a power supply path inside the semiconductor device; and (f) preparing a power supply model including impedance (par 47-48, 60, 69, 101-102, 112, 114, 117) information on a power supply path on the substrate.
(Claim 3) the steps (b), (c) and (d) are performed again (see loop/iteration process in fig 1-2) after a design of the electronic device is changed based on a result of simulating the EMI characteristics at the step (d).
(Claim 5) the steps (a) and (d) are performed again (see loop/iteration process in fig 1-2) after a design of the electronic device is changed based on a result of simulating the EMI characteristics at the step (d).
(Claim 7) the steps (a), (b), (c) and (d) are performed again (see loop/iteration process in fig 1-2)after a design of the electronic device is changed based on a result of simulating the EMI characteristics at the step (d).
(Claim 9) at the step (b) of measuring the power supply noise, power supply noises of a plurality of power supplies are measured at the same phase (par 70-75, 101)
Correspondence Information
Any inquiry concerning this communication or earlier communications from the examiner should be directed to PAUL DINH whose telephone number is 571-272-1890. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s Supervisor, Jack Chiang can be reached on 571-272-7483. The fax number for the organization where this application or proceeding is assigned is 571-273-8300.
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/PAUL DINH/ Primary Examiner, Art Unit 2851
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