DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Group I, claims 1-12, in the reply filed on 3/19/26 is acknowledged.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-12 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Chen et al. (US 2020/0152827).
Regarding claim 1, Chen discloses a display device, comprising:
a circuit substrate (SB, figs.3-4 and paragraph 0026) having a first sub-pixel (PXS1, fig.3 and paragraph 0028), a second sub-pixel (PXS2, fig. 3 and paragraph 0028), and a third sub-pixel (PXS3, fig.3 and paragraph 0028), wherein each of the first sub-pixel (PXS1, fig.3 and paragraph 0028), the second sub-pixel (PXS2, fig. 3 and paragraph 0028), and the third sub-pixel (PXS3, fig.3 and paragraph 0028), has a first bonding area (1021/102, figs.3-4 and paragraph 0028) and a second bonding area (1022/102, fig.3 and paragraph 0028);
a first light-emitting element (EU/EU1, fig.3 and paragraph 0028) located in the first bonding area (1021, fig.3 and paragraph 0028) of the first sub-pixel (PXS1, fig.3 and paragraph 0028) and bonded to the circuit substrate (SB, figs.3-4, paragraph and 0027) through a first solder structure (MT1, fig.4 and paragraph 0029);
a second light-emitting element (EU2, fig.3 and paragraph 0028) located in the second sub-pixel(PXS2, fig. 3 and paragraph 0028); and
a third light-emitting element (EU3, fig.3 and paragraph 0028) located on one of the first bonding area (1021, 102 figs.3-4 and paragraph 0028) and the second bonding area (1022, 102 figs.3-4 and paragraph 0028) of the third sub-pixel (PXS3, fig.3 and paragraph 0028) and bonded to the circuit substrate (SB, figs.3-4 and paragraph 0027) through a first conductive adhesive structure (MT1/MT2, fig.4 paragraph 0029-0032).
Regarding claim 2, Chen further discloses wherein the second light-emitting element (EU2/EUR, figs. 3-5 and paragraph 0028) is located in the second bonding area (1022,102 fig.3-4 and paragraph 0028) of the second sub- pixel (PXS2, fig. 3 and paragraph 0028), and is bonded to the circuit substrate (SB, figs.3-5 and paragraph 0027) through a second solder structure (MT1/MT2, figs. 4-5 and paragraphs 0029-0032), wherein there is a first residual solder (MT1, fig.4-5 and paragraph 0029-0032) on the first bonding area (102-right, figs. 4-5 paragraph 0032) of the second sub-pixel (PXS2, fig. 3 and paragraph 0028), and there is a second residual solder (MT1, fig.4-5 paragraph 0029-0032) on the other one of the first bonding area (102-right, figs. 4-5 paragraph 0032) and the second bonding area (102-right, figs. 4-5 paragraph 0032) of the third sub-pixel (PXS3, fig.3 paragraph 0028).
Regarding claim 3, Chen further discloses wherein the third light-emitting element (EU3, fig.3 and paragraph 0028) is disposed on the second bonding area (1022, 102-right, figs. 3-5 and paragraph 0032) of the third sub-pixel (PXS3, fig.3 and paragraph 0028), there is the second residual solder (MT1- left, fig.4-5 and paragraphs 0029-0032) on the first bonding area (1021, 102-left, figs. 3-5 and paragraph 0032) of the third sub-pixel (PXS3, fig.3 and paragraph 0028), and there is a third residual solder (MT1’, figs.4-5, 8 and paragraphs 0029-0032, 0037) separated from the second residual solder (MT1, figs.4-5 and paragraph 0029-0032) on the second bonding area of the third sub-pixel (PXS3, fig.3 and paragraph 0028).
Regarding claim 4, Chen further discloses wherein the third residual solder (MT1’, figs.4-5, 8 and paragraph 0029-0032, 0037) is in contact with the first conductive adhesive structure (MT1/MT2, figs.4, 8 and paragraph 0029-0032).
Regarding claim 5, Chen further discloses wherein the circuit substrate (SB, figs.3-4, and paragraph 0027) further includes a fourth sub-pixel (array shown -including multiple sub-pixels, fig.2 and paragraph 0031), each of the first sub-pixel (PXS1, fig.3 paragraph 0028), the second sub-pixel (PXS2, fig. 3 paragraph 0028), the third sub-pixel (PXS3, fig.3 paragraph 0028), and the fourth sub-pixel has the first bonding area and the second bonding area, and the display device further comprises: a fourth light-emitting element located on one of the first bonding area and the second bonding area of the fourth sub-pixel and bonded to the circuit substrate through a second conductive adhesive structure, wherein there is a residual conductive adhesive on the other one of the first bonding area and the second bonding area of the fourth sub-pixel (figs. 2-4).
Regarding claim 6, Chen further discloses a fourth residual solder located on the first bonding area of the fourth sub-pixel; and a fifth residual solder located on the second bonding area of the fourth sub-pixel (figs. 2-5).
Regarding claim 7, Chen further discloses wherein in each of the first sub-pixel, the second sub-pixel, and the third sub-pixel, the first bonding area is located in a first direction of the second bonding area (fig. 3).
Regarding claim 8, Chen further discloses wherein each of the first sub-pixel, the second sub-pixel, and the third sub-pixel comprises a first pad, a second pad, a first repair pad, and a second repair pad that are separated from one another, wherein the first pad and the second pad are disposed in the first bonding area, and the first repair pad and the second repair pad are disposed in the second bonding area (figs. 4-5).
Regarding claim 9, Chen further discloses wherein each of the first sub-pixel, the second sub-pixel, and the third sub-pixel comprises a first pad and a second pad that are separated from each other, wherein the first pad extends continuously from the first bonding area to the second bonding area, and the second pad extends continuously from the first bonding area to the second bonding area (fig. 3).
Regarding claim 10, Chen further discloses a flat layer located on the circuit substrate and surrounding the first light-emitting element and the second light-emitting element; a first interconnect structure located on the flat layer and electrically connected to the first light-emitting element (CL, fig. 3 and paragraph 0026); and a second interconnect structure located on the flat layer and electrically connected to the second light-emitting element (CL, fig. 3 and paragraph 0026).
Regarding claim 11, Chen further discloses wherein the first interconnect structure is connected to the second interconnect structure (common line, CL, fig. 3 and paragraph 0026-0028).
Regarding claim 12, Chen further discloses a plurality of conductive blocks disposed in the first sub-pixel and the second sub-pixel, wherein the first interconnect structure is electrically connected to the first light-emitting element and at least one of the conductive blocks, and the second interconnect structure is electrically connected to the second light-emitting element and the first interconnect structure (common line, CL, fig. 3 and paragraph 0026-0028).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. US Patent 10121710 discloses a display device with a method of repairing LEDs.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DOUGLAS M MENZ whose telephone number is (571)272-1877. The examiner can normally be reached Monday-Friday 8:00am-5:00pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jacob Choi can be reached at 469-295-9060. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/DOUGLAS M MENZ/Primary Examiner, Art Unit 2897 5/1/26
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