Prosecution Insights
Last updated: July 17, 2026
Application No. 18/544,560

INTEGRATED CIRCUIT DEVICE

Non-Final OA §103§112
Filed
Dec 19, 2023
Priority
Mar 24, 2023 — RE 10-2023-0038968 +1 more
Examiner
SHAMSUZZAMAN, MOHAMMED
Art Unit
2897
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Samsung Electronics Co., Ltd.
OA Round
1 (Non-Final)
81%
Grant Probability
Favorable
1-2
OA Rounds
0m
Est. Remaining
99%
With Interview

Examiner Intelligence

Grants 81% — above average
81%
Career Allowance Rate
738 granted / 911 resolved
+13.0% vs TC avg
Strong +55% interview lift
Without
With
+55.3%
Interview Lift
resolved cases with interview
Typical timeline
2y 5m
Avg Prosecution
37 currently pending
Career history
935
Total Applications
across all art units

Statute-Specific Performance

§103
93.0%
+53.0% vs TC avg
§102
2.4%
-37.6% vs TC avg
§112
2.0%
-38.0% vs TC avg
Black line = Tech Center average estimate • Based on career data from 911 resolved cases

Office Action

§103 §112
Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Election/Restrictions Applicant’s election of Species I , claims 1-10, in the reply filed on 05/22/2026 is acknowledged. Because applicant did not distinctly and specifically point out the supposed errors in the restriction requirement, the election has been treated as an election without traverse (MPEP § 818.01(a)). Claim Rejections - 35 USC § 112 The following is a quotation of 35 U.S.C. 112(b): (b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. Claims 1-10 are rejected under 35 U.S.C. 112(b), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor regards as the invention. Claim 1 recites “a gate line extending ..crossing.. the first through fourth fin-type active regions” is indefinite. As sown in Fig. 1, one gate line crossing either first and third or second and fourth active regions and multiple gate lines are crossing the first through fourth fin-type active regions. Appropriate correction is required. Claims 2-10 are also rejected being dependent on rejected claim 1. Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claims 1-3, 10 are rejected under 35 U.S.C. 103 as being obvious over Lee et al (US 2020/0119150 A1). Regarding claim 1: Lee teaches in Fig. 1, 2A-2D about an integrated circuit device comprising: PNG media_image1.png 674 1197 media_image1.png Greyscale a substrate 100 including a first device region AX and a second device region BX; a first fin-type active region F1 and a third fin-type active region F3 extending in a first horizontal direction (X) in the first device region; a second fin-type active region F2 and a fourth fin-type active region F4 extending in the first horizontal direction (X) in the second device region; a gate line 110 extending in a second horizontal direction (Y) crossing the first horizontal direction in the first through fourth fin-type active regions; a first source/drain region SDP (Fig. 2A) arranged adjacent to the gate line in the first fin-type active region; a second source/drain region arranged adjacent to the gate line in the second fin-type active region; a first source/drain contact 310 extending in a vertical direction (Z) in the first device region (Fig. 2A), and connected to the first source/drain region, wherein the vertical direction is substantially perpendicular to the first horizontal direction and the second horizontal direction; and a second source/drain contact extending in the vertical direction in the second device region, and connected to the second source/drain region; wherein the first source/drain contact comprises a first short metal plug 310 and a first conductive barrier layer 320 at least partially surrounding a portion of sidewalls of the first short metal plug (As shown). Lee does not explicitly show a second source/drain region arranged adjacent to the gate line in the second fin-type active region, a second source/drain contact extending in the vertical direction in the second device region, and connected to the second source/drain region; However Lee shows in Fig. 1 (top view) about the second device region BX as marked and extending the cross-sectional view (I-I’) to the right most SCP region would show a second source/drain region associated with the rightmost SCP region arranged adjacent to the gate line in the second fin-type active region, a second source/drain contact extending in the vertical direction in the second device region, and connected to the second source/drain region similar to Fig. 2A. Therefore, it would have been obvious to one of ordinary skill in the art at the time the application was filed to have the feature as claimed from Lee’s top view of Fig. 1 to have device regions with associated source/drain regions and their respective contacts for the integrated circuit device to have access for electrical connection to operate the device functionally. Regarding claim 2: Lee teaches in Fig. 2A wherein the first conductive barrier layer 320 is arranged between the first source/drain region SDP and the short metal plug 310. Regarding claim 3: Lee teaches in Fig. 2D wherein a vertical level of an uppermost surface of the first conductive barrier layer is higher than a vertical level of an uppermost surface of the gate line. PNG media_image2.png 612 750 media_image2.png Greyscale Regarding claim 10: Lee further teaches in Fig. 2A about further comprising an inter-gate insulating layer 140 arranged in the first source/drain region SDP, wherein the first source/drain contact penetrates an uppermost surface in the first source/drain region (as shown), and an upper portion of sidewalls of the first source/drain contact is at least partially surrounded by the inter-gate insulating layer (as shown). Claims 4, 8-9 are rejected under 35 U.S.C. 103 as being obvious over Lee et al (US 2020/0119150 A1) in view of Jung et al. (US 20180182756 A1) Regarding claim 4: Lee teaches wherein the gate line comprises: a first gate line 110 extending in the second horizontal direction in the first device region; and a second gate line (another 110) extending in the second horizontal direction in the second device region, wherein a width, in a first horizontal direction, of the first gate line is less than a width, in the first horizontal direction, of the second gate line. Lee does not teach wherein a width, in a first horizontal direction, of the first gate line is less than a width, in the first horizontal direction, of the second gate line. Jung teaches in Fig. 1 wherein a width, in a first horizontal direction, of the first gate line GL2 is less than a width, in the first horizontal direction, of the second gate line GL1 Therefore, it would have been obvious to one of ordinary skill in the art at the time the application was filed to have the feature as claimed from Jung’s teachings depending on device type/function (Jung, [0026]). Regarding claim 8: Lee does not teach wherein a length, in the vertical direction, of the first source/drain contact is less than a length, in the vertical direction, of the second source/drain contact. Jung teaches in Fig. 2B, 8A, 8B and [0088] – [0092] , the height of the first source/drain 130A, second source/drain 130B are different and therefore the contact plugs CP1, CP2 heights would be different. Therefore, it would have been obvious to one of ordinary skill in the art at the time the application was filed to have the feature as claimed from Jung’s teachings depending on device type/function (Jung, [0026]). Regarding claim 9: Jung teaches in Fig. 9A further comprising a source/drain via contact VC2 extending in a vertical direction and disposed on the second source/drain contact in the second device region. Claim 5 is rejected under 35 U.S.C. 103 as being obvious over Lee et al (US 2020/0119150 A1) in view of More et al. (TW 202221770 A) Regarding claim 5: Lee does not teach wherein a width, in the first horizontal direction, of the first source/drain region is less than a width, in the first horizontal direction, of the second source/drain region. More teaches in Fig. 3-4 about wherein a width S1a, in the first horizontal direction, of the first source/drain region (for N type) is less than a width S1b, in the first horizontal direction, of the second source/drain region (P type). Therefore, it would have been obvious to one of ordinary skill in the art at the time the application was filed to have the feature as claimed from More’s teachings depending on device type either n type or p type and to avoid short circuits with adjacent structures. Allowable Subject Matter Claim 6 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. The limitation allowable is “wherein the second source/drain contact comprises a long metal plug and a second conductive barrier layer, wherein the second conductive barrier layer surrounds sidewalls of the long metal plug, and wherein the second conductive barrier layer comprises a first lower portion layer and a second lower portion layer, wherein the first lower portion layer covers a lowermost surface of the long metal plug, and the second lower layer extends in the first horizontal direction on the first lower portion layer” in combination with other limitations as a whole. Claim 7 is also allowable being dependent on allowable claim 6 Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to MOHAMMED SHAMSUZZAMAN whose telephone number is (571)270-1839. The examiner can normally be reached Monday-Friday 7 am -4 pm EST. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Fernando Toledo can be reached at 571-272-1867. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /Mohammed Shamsuzzaman/Primary Examiner, Art Unit 2897
Read full office action

Prosecution Timeline

Dec 19, 2023
Application Filed
Jun 25, 2026
Non-Final Rejection mailed — §103, §112 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
81%
Grant Probability
99%
With Interview (+55.3%)
2y 5m (~0m remaining)
Median Time to Grant
Low
PTA Risk
Based on 911 resolved cases by this examiner. Grant probability derived from career allowance rate.

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