CTNF 18/544,670 CTNF 83782 DETAILED ACTION Notice of Pre-AIA or AIA Status 07-03-aia AIA 15-10-aia The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Election/Restrictions Applicant’s election without traverse of Species 1, claims 1-3, 6 and 8-14 in the reply filed on April 27, 2026 is acknowledged. Claims 4, 5, 7 and 15-20 have been withdrawn. Action on the merits is as follows: Claim Rejections - 35 USC § 102 07-06 AIA 15-10-15 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. 07-07-aia AIA 07-07 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – 07-08-aia AIA (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. 07-15-aia AIA Claim(s) 1-3, 6 and 8-14 is/are rejected under 35 U.S.C. 102 (a)(1) as being anticipated by Lee et al. (Lee) (US 2023/0307448 A1) . In regards to claim 1 , Lee (Figs. 1-4C, 16B, 18, 19 and associated text and items) discloses a three-dimensional (3D) semiconductor device (Fig. 3) , comprising: a substrate (item 100) including a first surface (top or bottom surface of item 100) and a second surface (top or bottom surface of item 100) that are opposite to each other; a lower active region (item AR1) on the first surface of the substrate (item 100) , the lower active region (item AR1) comprising a lower channel pattern (item CH1) and a lower source/drain pattern (item SD1) that are electrically connected to each other; an upper active region (item AR2) on the lower active region (item AR1) , the upper active region (item AR2) comprising an upper channel pattern (item CH2) and an upper source/drain pattern (item SD2) that are electrically connected to each other; a dam pattern (items LSS plus USS) that vertically extends from the lower source/drain pattern (item SD!) to the upper source/drain pattern (item SD2) ; a lower active contact (lower portions of items AC1, AC2, AC3, AC4 or item AP) electrically connected to the lower source/drain pattern (item SD1) ; an upper active contact (upper portions of items AC1, AC2, AC3, AC4 or item CNL) electrically connected to the upper source/drain pattern (item SD2) ; and a vertical via (middle portions of items AC1, AC2, AC3 or AC4 or items AC1, AC2, AC3, AC4) that vertically extends along the dam pattern (items LSS plus USS) to electrically connect the lower active contact (lower portions of items AC1, AC2, AC3, AC4 or item AP) to the upper active contact (upper portions of items AC1, AC2, AC3, AC4 or item CNL) , wherein the dam pattern (items LSS plus USS) comprises a first dam pattern (items LSS or USS) and a second dam pattern (items LSS or USS) , wherein the lower source/drain pattern (item SD1) is between the first and second dam patterns (items LSS and USS) , and wherein the upper source/drain pattern (item SD2) is between the first and second dam patterns (items LSS and USS) . In regards to claim 2 , Lee (Figs. 1-4C, 16B, 18, 19 and associated text and items) discloses further comprising a gate electrode (item GE) on the lower channel pattern (item CH1) and the upper channel pattern (item CH2) , wherein the gate electrode (item GE) is between the first and second dam patterns (items LSS and USS) . In regards to claim 3 , Lee (Figs. 1-4C, 16B, 18, 19 and associated text and items) discloses wherein each of the lower and upper channel patterns (items CH1 and CH2) comprises a plurality of semiconductor patterns (items SP1-SP6) that are vertically stacked and spaced apart from each other, and wherein the gate electrode (item GE) comprises: a lower gate electrode (item LGE) surrounding the semiconductor patterns (items SP1-SP3) of the lower channel pattern (item CH1) ; and an upper gate electrode (item UGE) surrounding the semiconductor patterns (items Sp4-SP6 ) of the upper channel pattern (item CH2) . In regards to claim 6 , Lee (Figs. 1-4C, 16B, 18, 19 and associated text and items) discloses further comprising: a first metal layer (items CNL, VI or MI3) on the upper active contact (upper portions of items AC1, AC2, AC3, AC4 or item CNL) ; and a back-side metal layer (item LMI or vias shown but not labeled) on the second surface of the substrate (item 100) . In regards to claim 8 , Lee (paragraph 56, Figs. 1-4C, 16B, 18, 19 and associated text and items) discloses further comprising a dummy channel pattern (item DSP) between the lower channel pattern (item CH1) and the upper channel pattern (item CH2) , wherein the dummy channel pattern (item DSP) is spaced apart from the lower source/drain pattern (item SD1) and the upper source/drain pattern (item SD2) . In regards to claim 9 , Lee (paragraph 56, Figs. 1-4C, 16B, 18, 19 and associated text and items) discloses wherein the lower source/drain pattern (item SD1) has a first conductivity type (n-type or p-type, paragraph 52) , and wherein the upper source/drain pattern (item SD2) has a second conductivity type (n-type or p-type, paragraph 58) different from the first conductivity type (n-type or p-type, paragraph 58) . In regards to claim 10 , Lee (paragraph 46, Figs. 1-4C, 16B, 18, 19 and associated text and items) discloses wherein the lower active region (item AR1) and the upper active region (item AR2) constitute a logic cell (item LC, paragraph 46) , and wherein the first and second dam patterns (items LSS and USS) define opposite borders of the logic cell (item LC) . In regards to claim 11 , Lee (Figs. 1-4C, 16B, 18, 19 and associated text and items) discloses a three-dimensional (3D) semiconductor device (Fig. 3) , comprising a substrate (item 100) including a first surface (top or bottom surface of item 100) and a second surface (top or bottom surface of item 100) that are opposite to each other; logic cells (item LC, AR1 plus AR2, paragraph 91) arranged on the first surface of the substrate (item 100) in a first direction (D2) ; and a cutting pattern (item CT) that is between adjacent ones of the logic cells (item LC, AR1 plus AR2) and extends in a second direction (D1) crossing the first direction (D2) , wherein each of the logic cells (item LC, AR1 plus AR2, paragraph 91) comprises: a lower active region (item AR1) comprising a lower channel pattern (item CH1) and a lower source/drain pattern (item SD1) that are electrically connected to each other; an upper active region (item AR2) on the lower active region (item AR1) , the upper active region (item AR2) comprising an upper channel pattern (item CH2) and an upper source/drain pattern (item SD2) that are electrically connected to each other; and a gate electrode (item GE) on the lower and upper channel patterns (item CH1 and CH2) , wherein at least a portion of the cutting pattern (item CT) extends in the second direction (D1) adjacent to the gate electrode (item GE) , and wherein the cutting pattern (item CT) comprises a pair of dam patterns (items LSS and USS) that vertically extend and an insulating gapfill layer (portions of items 110 and 120) that is between the pair of dam patterns (items LSS and USS) . In regards to claim 12 , Lee (Figs. 1-4C, 16B, 18, 19 and associated text and items) discloses further comprising: a lower active contact (lower portions of items AC1, AC2, AC3, AC4 or item AP) electrically connected to the lower source/drain pattern (item SD1) ; an upper active contact (upper portions of items AC1, AC2, AC3, AC4 or item CNL) electrically connected to the upper source/drain pattern (item SD2) ; and a vertical via in the cutting pattern (item CT) , wherein the vertical via (middle portions of items AC1, AC2, AC3 or AC4 or items AC1, AC2, AC3, AC4) electrically connects the lower active contact (lower portions of items AC1, AC2, AC3, AC4 or item AP) to the upper active contact (upper portions of items AC1, AC2, AC3, AC4 or item CNL) . In regards to claim 13 , Lee (Figs. 1-4C, 16B, 18, 19 and associated text and items) discloses further comprising: a first metal layer (items CNL, VI or MI3) on the upper active contact (upper portions of items AC1, AC2, AC3, AC4 or item CNL) ; and a back-side metal layer (item LMI or vias shown but not labeled) on the second surface of the substrate (item 100) . In regards to claim 14 , Lee (Figs. 1-4C, 16B, 18, 19 and associated text and items) discloses wherein the cutting pattern ( item CT) is configured to prevent the lower and upper source/drain patterns (items SD1 and SD2) from expanding to a region beyond respective ones of the logic cells (item LC, paragraph 71) . Conclusion 07-96 AIA The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Park et al. (KR 20230063899 A) discloses all of the limitations of independent claims 1 and 11 except for upper and lower dam patterns . Any inquiry concerning this communication or earlier communications from the examiner should be directed to TELLY D GREEN whose telephone number is (571)270-3204. The examiner can normally be reached M-F 8am-5pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jessica Manno can be reached at 571-272-2339. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. TELLY D. GREEN Examiner Art Unit 2898 /TELLY D GREEN/Primary Examiner, Art Unit 2898 June 11, 2026 Application/Control Number: 18/544,670 Page 2 Art Unit: 2898 Application/Control Number: 18/544,670 Page 3 Art Unit: 2898 Application/Control Number: 18/544,670 Page 4 Art Unit: 2898 Application/Control Number: 18/544,670 Page 5 Art Unit: 2898 Application/Control Number: 18/544,670 Page 6 Art Unit: 2898 Application/Control Number: 18/544,670 Page 7 Art Unit: 2898
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