Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1, 11 and 17 are the independent claims.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 2, 8, 9, 10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Guler et al. (hereinafter Guler, US 2023/0317787) in view of Hwang et al. (hereinafter Hwang, US 2023/0046885).
In regards to independent claim 1, Guler teaches a semiconductor device, comprising:
a bottom layer including a pair of first channel regions (see Fig. 1F, channel regions 112 the center and on the right) separated by a first dielectric bar ( the right 144, 106B), a pair of second channel regions (channel regions 112 center and left) separated by a second dielectric bar (The left 114 106B), and a gate structure (143A) having an integral backside contact (172) between the first channel regions and the second channel regions (Guler, Fig. 1F).
Guler fails to teach:
a top layer including third channel regions, over and laterally offset with respect to the first channel regions, and fourth channel regions, over and laterally offset with respect to the second channel regions.
Hwang teaches:
a top layer including third channel regions (Fig. 3B, 315C), over and laterally offset with respect to the first channel regions (Fig. 3B 305C), and fourth channel regions, over and laterally offset with respect to the second channel regions (The channels shown in Fig. 3B are repeated as shown in Fig. 3A) (Hwang, Fgi. 3A, 3B, [0057] discusses the application to FinFets).
It would have been obvious to one of ordinary skill in the art, having the teachings of Guler and Hwang before him before the effective filing date of the claimed invention, to modify the nanowire FinFET taught by Guler to include the top layer channels of Hwang in order to obtain a nanowire FinFET that has bottom and top layer channels. One would have been motivated to make such a combination because it would increase transistor density by have a top and bottom layer.
In regards to dependent claim 2, Guler teaches the semiconductor device of claim 1, wherein a lateral distance between the first channel regions and the second channel regions is greater than a space between the pair of first channel regions and a space between the pair of second channel regions (Guler, Fig. 1F, wider channel spacing at backside gate contact).
In regards to dependent claim 8, Guler teaches the semiconductor device of claim 1, wherein the bottom layer further includes first source/drain regions epitaxially grown from side surfaces of the first channel regions and second source/drain regions epitaxially grown from side surfaces of the second channel regions (Gular, [0035]).
In regards to dependent claim 9, Guler teaches the semiconductor device of claim 8, wherein the first dielectric bar further separates the first source/drain regions and the second dielectric bar further separates the second source/drain regions (Guler, Fig. 1E, 144 separates 128).
In regards to dependent claim 10, Hwang teaches wherein the top layer is bonded to the bottom layer by a bonding oxide layer (Hwang, [0042]).
Claim(s) 3, 4, 7, 11, 12-14, 16, is/are rejected under 35 U.S.C. 103 as being unpatentable over Guler in view of Hwang and Hsu (Hsu, US 2023/0154847).
In regards to dependent claim 3, Guler fails to explicitly teach frontside back-end-of-line (BEOL) layers over the top layer and backside BEOL layers under the bottom layer. Hsu teaches frontside back-end-of-line (BEOL) layers over the top layer and backside BEOL layers under the bottom layer (Hsu, [0054], [0057]). It would have been obvious to one of ordinary skill in the art, having the teachings of Guler and Hwang and Hsu before him before the effective filing date of the claimed invention, to modify the nanowire FinFET taught by Guler to include the BEOL layer above the top layer and below the bottom layer of Hsu in order to obtain a nanowire FinFET that has BEOL layers above and below the top and bottom channels respectively. One would have been motivated to make such a combination because it reduces the number of inter-layer vias required thereby allowing higher transistor density and less interference.
In regards to dependent claim 4, Hsu teaches wherein the frontside BEOL layers and the backside BEOL layers both include power and signal interconnects (Hsu, [0026], [0027]). It would have been obvious to one of ordinary skill in the art, having the teachings of Guler and Hwang and Hsu before him before the effective filing date of the claimed invention, to modify the nanowire FinFET taught by Guler to include the BEOL layer above the top layer and below the bottom layer of Hsu in order to obtain a nanowire FinFET that has BEOL layers above and below the top and bottom channels respectively. One would have been motivated to make such a combination because it reduces the number of inter-layer vias required thereby allowing higher transistor density and less interference.
In regards to dependent claim 7, Hsu teaches wherein first channel regions and the second channel region include semiconductor nanosheets that directly contact the respective first dielectric bar and second dielectric bar (Hsu, Fig. 2D 115a contact isolation wall 119a). It would have been obvious to one of ordinary skill in the art, having the teachings of Guler and Hwang and Hsu before him before the effective filing date of the claimed invention, to modify the nanowire FinFET taught by Guler to include the BEOL layer above the top layer and below the bottom layer of Hsu in order to obtain a nanowire FinFET that has BEOL layers above and below the top and bottom channels respectively. One would have been motivated to make such a combination because it reduces the number of inter-layer vias required thereby allowing higher transistor density and less interference.
In regards to independent claim 11, Guler teaches a semiconductor device, comprising:
a bottom layer including a pair of first channel regions having first channels (see Fig. 1F, channel regions 112 the center and on the right) separated by and directly contacting a first dielectric bar ( the right 144, 106B), a pair of second channel regions having second channels (channel regions 112 center and left) separated by and directly contacting a second dielectric bar (The left 114 106B),
and a gate structure (143A) having an integral backside contact (172). (Guler, Fig. 1F);
Guler fails to explicitly teach:
a top layer including third channel regions, over and laterally offset with respect to the first channel regions, and fourth channel regions, over and laterally offset with respect to the second channel regions.
a gate structure having an integral backside contact between the first channel regions and the second channel regions, wherein a lateral distance between the first channel regions and the second channel regions is greater than a space between the pair of first channel regions and a space between the pair of second channel regions; and wherein structures of the bottom layer and structures of the top layer are electrically isolated from each other
Hwang teaches:
a top layer including third channel regions (Fig. 3B, 315C), over and laterally offset (Fig. 3B 305C) with respect to the first channel regions, and fourth channel regions, over and laterally offset with respect to the second channel regions, (The channels shown in Fig. 3B are repeated as shown in Fig. 3A) (Hwang, Fgi. 3A, 3B, [0057] discusses the application to FinFets).
It would have been obvious to one of ordinary skill in the art, having the teachings of Guler and Hwang before him before the effective filing date of the claimed invention, to modify the nanowire FinFET taught by Guler to include the top layer channels of Hwang in order to obtain a nanowire FinFET that has bottom and top layer channels. One would have been motivated to make such a combination because it would increase transistor density by have a top and bottom layer.
Hsu teaches:
a gate structure (108b) having an integral backside contact (113g) between the first channel regions and the second channel regions (regions around 108a, 108b and 108c, 108d), wherein a lateral distance between the first channel regions and the second channel regions is greater than a space between the pair of first channel regions and a space between the pair of second channel regions (Space between channels formed by 108 vs 108d) is farther than the distance from the channels formed by 108a, 108b); and wherein structures of the bottom layer and structures of the top layer are electrically isolated from each other (Hsu, Fig. 2D, 101, 103 are separated from 102, 104).
It would have been obvious to one of ordinary skill in the art, having the teachings of Guler and Hwang and Hsu before him before the effective filing date of the claimed invention, to modify the nanowire FinFET taught by Guler to include the BEOL layer above the top layer and below the bottom layer of Hsu in order to obtain a nanowire FinFET that has BEOL layers above and below the top and bottom channels respectively. One would have been motivated to make such a combination because it reduces the number of inter-layer vias required thereby allowing higher transistor density and less interference.
In regards to dependent claim 12, Hsu teaches frontside back-end-of-line (BEOL) layers over the top layer and backside BEOL layers under the bottom layer (Hsu, [0054], [0057]). It would have been obvious to one of ordinary skill in the art, having the teachings of Guler and Hwang and Hsu before him before the effective filing date of the claimed invention, to modify the nanowire FinFET taught by Guler to include the BEOL layer above the top layer and below the bottom layer of Hsu in order to obtain a nanowire FinFET that has BEOL layers above and below the top and bottom channels respectively. One would have been motivated to make such a combination because it reduces the number of inter-layer vias required thereby allowing higher transistor density and less interference.
In regards to dependent claim 13, Hsu teaches wherein the frontside BEOL layers and the backside BEOL layers both include power and signal interconnects (Hsu, [0026], [0027]). It would have been obvious to one of ordinary skill in the art, having the teachings of Guler and Hwang and Hsu before him before the effective filing date of the claimed invention, to modify the nanowire FinFET taught by Guler to include the BEOL layer above the top layer and below the bottom layer of Hsu in order to obtain a nanowire FinFET that has BEOL layers above and below the top and bottom channels respectively. One would have been motivated to make such a combination because it reduces the number of inter-layer vias required thereby allowing higher transistor density and less interference.
In regards to dependent claim 14, Guler teaches wherein the bottom layer further includes first source/drain regions epitaxially grown from side surfaces of the first channel regions and second source/drain regions epitaxially grown from side surfaces of the second channel regions (Gular, [0035]).
In regards to dependent claim 16, Guler teaches wherein the first dielectric bar further separates the first source/drain regions and the second dielectric bar further separates the second source/drain regions (Guler, Fig. 1E, 144 separates 128).
Claim(s) 5, 6, 14, 17-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Guler in view of Hwang and Hsu and Chanemougame et al. (hereinafter Chanemougame, US 2022/0271033)
In regards to dependent claim 5, Guler fails to explicitly teach comprising an inter-layer via that connects the frontside BEOL layers to the backside BEOL layers. Chanemougame teaches further comprising an inter-layer via that connects the frontside BEOL layers to the backside BEOL layers (Chanemougame, Fig. 7c, 770). It would have been obvious to one of ordinary skill in the art, having the teachings of Guler and Hwang and Hsu and Chanemougame before him before the effective filing date of the claimed invention, to modify the nanowire FinFET taught by Guler to include inter-layer via of Chanemougame in order to obtain a nanowire FinFET that has inter-layer vias to connect top and bottom BEOL. One would have been motivated to make such a combination because it ensures that common power lines such as VDD are at the same potential for both top and bottom channel regions.
In regards to dependent claim 6, Guler fails to explicitly teach wherein structures of the bottom layer and structures of the top layer are electrically isolated. Chanemougame teaches wherein structures of the bottom layer and structures of the top layer are electrically isolated (Hsu, Fig. 2A, 2D, no connection). It would have been obvious to one of ordinary skill in the art, having the teachings of Guler and Hwang and Hsu and Chanemougame before him before the effective filing date of the claimed invention, to modify the nanowire FinFET taught by Guler to include inter-layer via of Chanemougame in order to obtain a nanowire FinFET that has inter-layer vias to connect top and bottom BEOL. One would have been motivated to make such a combination because it ensures that common power lines such as VDD are at the same potential for both top and bottom channel regions.
In regards to dependent claim 14, Guler fails to explicitly teach an inter-layer via that connects the frontside BEOL layers to the backside BEOL layers. Chanemougame teaches an inter-layer via that connects the frontside BEOL layers to the backside BEOL layers (Chanemougame, Fig. 7c, 770). It would have been obvious to one of ordinary skill in the art, having the teachings of Guler and Hwang and Hsu and Chanemougame before him before the effective filing date of the claimed invention, to modify the nanowire FinFET taught by Guler to include inter-layer via of Chanemougame in order to obtain a nanowire FinFET that has inter-layer vias to connect top and bottom BEOL. One would have been motivated to make such a combination because it ensures that common power lines such as VDD are at the same potential for both top and bottom channel regions.
In regards to independent claim 17, Guler teaches a semiconductor device, comprising:
a bottom layer comprising a pair of first channel regions having first channels (see Fig. 1F, channel regions 112 the center and on the right) being separated by and directly contacting a first dielectric bar ( the right 144, 106B), a pair of second channel regions having second channels (channel regions 112 center and left) being separated by and directly contacting a second dielectric bar (The left 114 106B), and
Guler fails to explicitly teach:
a gate structure having an integral backside contact between the first channel regions and the second channel regions, wherein a lateral distance between the first channel regions and the second channel regions is greater than a space between the pair of first channel regions and a space between the pair of second channel regions;
backside back-end-of-line (BEOL) layers under the bottom layer
a top layer comprising third channel regions over and laterally offset with respect to the first channel regions and fourth channel regions, over and laterally offset with respect to the second channel regions,
wherein structures of the bottom layer and structures of the top layer are electrically isolated from each other;
frontside BEOL layers over the top layer
an inter-layer via that connects the frontside BEOL layers to the backside BEOL layers
Hwang teaches:
a top layer comprising third channel regions (Fig. 3B, 315C), over and laterally offset with respect to the first channel regions (Fig. 3B 305C), and fourth channel regions, over and laterally offset with respect to the second channel regions, (The channels shown in Fig. 3B are repeated as shown in Fig. 3A) (Hwang, Fgi. 3A, 3B, [0057] discusses the application to FinFets)
It would have been obvious to one of ordinary skill in the art, having the teachings of Guler and Hwang before him before the effective filing date of the claimed invention, to modify the nanowire FinFET taught by Guler to include the top layer channels of Hwang in order to obtain a nanowire FinFET that has bottom and top layer channels. One would have been motivated to make such a combination because it would increase transistor density by have a top and bottom layer.
Hsu teaches
a gate structure (108b) having an integral backside contact (113g) between the first channel regions and the second channel regions (regions around 108a, 108b and 108c, 108d), wherein a lateral distance between the first channel regions and the second channel regions is greater than a space between the pair of first channel regions and a space between the pair of second channel regions (Space between channels formed by 108 vs 108d) is farther thand the distance from the channels foremed by 108a, 108b); and wherein structures of the bottom layer and structures of the top layer are electrically isolated from each other (Hsu, Fig. 2D, 101, 103 are separated from 102, 104)
backside back-end-of-line (BEOL) layers under the bottom layer (Hsu, [0054], [0057]);
wherein structures of the bottom layer and structures of the top layer are electrically isolated from each other; (Hsu, Fig. 2D, 101, 103 are separated from 102, 104);
frontside BEOL layers over the top layer (Hsu, [0054], [0057]).
It would have been obvious to one of ordinary skill in the art, having the teachings of Guler and Hwang and Hsu before him before the effective filing date of the claimed invention, to modify the nanowire FinFET taught by Guler to include the BEOL layer above the top layer and below the bottom layer of Hsu in order to obtain a nanowire FinFET that has BEOL layers above and below the top and bottom channels respectively. One would have been motivated to make such a combination because it reduces the number of inter-layer vias required thereby allowing higher transistor density and less interference.
Chanemougame teaches:
an inter-layer via that connects the frontside BEOL layers to the backside BEOL layers (Chanemougame, Fig. 7c, 770).
It would have been obvious to one of ordinary skill in the art, having the teachings of Guler and Hwang and Hsu and Chanemougame before him before the effective filing date of the claimed invention, to modify the nanowire FinFET taught by Guler to include inter-layer via of Chanemougame in order to obtain a nanowire FinFET that has inter-layer vias to connect top and bottom BEOL. One would have been motivated to make such a combination because it ensures that common power lines such as VDD are at the same potential for both top and bottom channel regions.
In regards to dependent claim 18, Hsu teaches the semiconductor device of claim 17, wherein the frontside BEOL layers and the backside BEOL layers both include power and signal interconnects (Hsu, [0026], [0027]). It would have been obvious to one of ordinary skill in the art, having the teachings of Guler and Hwang and Hsu before him before the effective filing date of the claimed invention, to modify the nanowire FinFET taught by Guler to include the BEOL layer above the top layer and below the bottom layer of Hsu in order to obtain a nanowire FinFET that has BEOL layers above and below the top and bottom channels respectively. One would have been motivated to make such a combination because it reduces the number of inter-layer vias required thereby allowing higher transistor density and less interference.
In regards to dependent claim 19, Guler teaches wherein the bottom layer further includes first source/drain regions epitaxially grown from side surfaces of the first channel regions and second source/drain regions epitaxially grown from side surfaces of the second channel regions (Gul2r, [0035]).
In regards to dependent claim 20, Guler teaches wherein the first dielectric bar further separates the first source/drain regions and the second dielectric bar further separates the second source/drain regions (Guler, Fig. 1E, 144 separates 128).
Conclusion
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/WILLIAM C TRAPANESE/Primary Examiner, Art Unit 2812