DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant's election with traverse of Group I, Species 1 in the reply filed on 2/25/26 is acknowledged. The traversal is on the ground(s) that the species are not mutually exclusive and it would not be a burdensome search upon the office to examine all claims. This is not found persuasive because an exhaustive search has been conducted upon the elected species and the best prior art has been identified to address the elected species- the prior art, Chen, does not anticipate the non-elected species subject matter and would require the office to conduct a second burdensome search to address the non-elected species. Applicant is reminded that should future prosecution result in the identification of allowable subject matter which is properly incorporated into the withdrawn claims; rejoinder may be possible.
The requirement is still deemed proper and is therefore made FINAL.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 3-4, 9 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 3 recites (emphasis added):
3. (Original) The semiconductor package of claim 2, wherein the second semiconductor chip includes a second connecting pad, and the second connecting pad faces the first redistribution line structure.
This is rendered indefinite by the language of claim 4, which recites:
4. (Original) The semiconductor package of claim 2, wherein the second semiconductor chip includes a second connecting pad, and the second connecting pad faces the second redistribution line structure.
In efforts to keep the claim language clear- different structural elements should be given different names- for example an upper second conductive pad; and a lower second conductive pad- but Applicant is reminded to be consistent with what is taught in the specification- but to name two different structural components- the same name creates a lack of clarity and a 112 problem. Appropriate correction is required.
In regards to claim 9, the claim recites (emphasis added):
9. (Currently Amended) The semiconductor package of claim 1, further comprising: an electronic element and on the other second surface of the first redistribution line structure, the electronic element spaced apart from the second semiconductor chip; and a third conductive bump between the first redistribution line structure and the electronic element to connect the first redistribution line structure and the electronic element.
The other second surface? This claim language is unclear and renders the claim indefinite. It is unclear what the “other” second surface means- the Examiner assumes the meaning to be another region of the second surface? And is examining in accordance with such an interpretation. Applicant’s correction should be made consistent with the teachings in the specification. Appropriate correction is requested.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-4, 7-11 is/are rejected under 35 U.S.C. 102a1 as being anticipated by Chen et al (US 10535597).
1. (Currently Amended) A semiconductor package comprising:
a first redistribution line structure (Fig.7C (520) and Col.9-10, lines: 60-5);
a first semiconductor chip (Fig. 7C (550) and Col.12, lines:55-65) on one a first surface (top) of the first redistribution line structure (Fig.7C (520) and Col.9-10, lines: 60-5);
a first conductive bump (Fig.7C (544) and Col.12, lines: 55-65) between the first redistribution line structure (Fig.7C (520) and Col.9-10, lines: 60-5) and the first semiconductor chip (Fig. 7C (550) and Col.12, lines:55-65) to connect the first redistribution line structure (Fig.7C (520) and Col.9-10, lines: 60-5) and the first semiconductor chip (Fig. 7C (550) and Col.12, lines:55-65);
a first encapsulant (Fig.7C (552) and Col. 13, lines: 10-25) encapsulating at least a portion of the first semiconductor chip (Fig. 7C (550) and Col.12, lines:55-65);
a second semiconductor chip (Fig.7C (703) and Col.15, lines: 40-50) on another a second surface (bottom) of the first redistribution line structure (Fig.7C (520) and Col.9-10, lines: 60-5) that is opposite to the one first surface (top) of the first redistribution line structure (Fig.7C (520) and Col.9-10, lines: 60-5), the second semiconductor chip (Fig.7C (703) and Col.15, lines: 40-50) including a through via (Fig. 7C (505) and Col.16, lines:10-15);
a second conductive bump (Fig.7B-7C (538) and (Col.15, lines: 40-55) between the first redistribution line structure (Fig.7C (520) and Col.9-10, lines: 60-5) and the second semiconductor chip (Fig.7C (703) and Col.15, lines: 40-50) to connect the first redistribution line structure (Fig.7C (520) and Col.9-10, lines: 60-5) and the second semiconductor chip (Fig.7C (703) and Col.15, lines: 40-50);
a second encapsulant (Fig.7C (518) and Col. 15, lines: 25-35) encapsulating at least a portion of the second semiconductor chip (Fig.7C (703) and Col.15, lines: 40-50); and
a second redistribution line structure (Fig.7C (542) and Col.15, lines: 5-15) on the second encapsulant (Fig.7C (518) and Col. 15, lines: 25-35), wherein the second encapsulant (Fig.7C (518) and Col. 15, lines: 25-35) covers at least a portion of a surface of the second semiconductor chip (Fig.7C (703) and Col.15, lines: 40-50) facing the second redistribution line structure (Fig.7C (542) and Col.15, lines: 5-15).
2. (Original) The semiconductor package of claim 1, wherein the first semiconductor chip (Fig. 7C (550) and Col.12, lines:55-65) includes a first connecting pad (Fig.7C (see annotated drawing below- label added) and Col.10, lines: 50-60), and the first connecting pad (Fig.7C (see annotated drawing below- label added) and Col.10, lines: 50-60) faces the first redistribution line structure(Fig.7C (520) and Col.9-10, lines: 60-5).
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3. (Original) The semiconductor package of claim 2, wherein the second semiconductor chip (Fig.7C (703) and Col.15, lines: 40-50) includes a second connecting pad (Fig.7C (see annotated drawing above- label added) and Col.10, lines: 50-60), and the second connecting pad (Fig.7C (see annotated drawing above- label added) faces the first redistribution line structure (Fig.7C (520) and Col.9-10, lines: 60-5).
4. (Original) The semiconductor package of claim 2, wherein the second semiconductor chip (Fig.7C (703) and Col.15, lines: 40-50) includes a second connecting pad (Fig.7C (see annotated drawing above- label added) and Col.10, lines: 50-60), and the second connecting pad (Fig.7C (see annotated drawing above- label added) and Col.10, lines: 50-60) faces the second redistribution line structure (Fig.7C (542) and Col.15, lines: 5-15).
7. (Original) The semiconductor package of claim 1, further comprising a via (Fig.7F (unlabeled- see annotated drawing below) and Col.15-16, Lines: 55-5) penetrating a portion of the second encapsulant (Fig.7C (518) and Col. 15, lines: 25-35) to electrically connect the second semiconductor chip (Fig.7C (703) and Col.15, lines: 40-50) and the second redistribution line structure (Fig.7C (542) and Col.15, lines: 5-15).
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8. (Original) The semiconductor package of claim 1, wherein the through via (Fig. 7C (505) and Col.16, lines:10-15) at least partially penetrates the second semiconductor chip (Fig.7C (703) and Col.15, lines: 40-50) to further penetrate a portion of the second encapsulant (Fig.7C (518) and Col. 15, lines: 25-35), and the through via (Fig. 7C (505) and Col.16, lines:10-15) electrically connects the second semiconductor chip (Fig.7C (703) and Col.15, lines: 40-50) and the second redistribution line structure (Fig.7C (542) and Col.15, lines: 5-15).
9. (Currently Amended) The semiconductor package of claim 1, further comprising: an electronic element (Fig.7C (704/502) and Col.14, lines: 50-60) and on the other second surface (bottom) of the first redistribution line structure (Fig.7C (520) and Col.9-10, lines: 60-5), the electronic element (Fig.7C (704/502) and Col.14, lines: 50-60) spaced apart from the second semiconductor chip (Fig.7C (703) and Col.15, lines: 40-50); and
a third conductive bump (Fig.7B-7C (508/548) and (Col.15, lines: 40-55) between the first redistribution line structure (Fig.7C (520) and Col.9-10, lines: 60-5) and the electronic element (Fig.7C (704/502) and Col.14, lines: 50-60) to connect the first redistribution line structure (Fig.7C (520) and Col.9-10, lines: 60-5) and the electronic element (Fig.7C (704/502) and Col.14, lines: 50-60).
10. (Currently Amended) The semiconductor package of claim 1, wherein the first redistribution line structure (Fig.7C (520) and Col.9-10, lines: 60-5) includes a redistribution line layer (Fig.5A (520/503) exposed to a the second surface of the first redistribution line (Fig.7C (520) and Col.9-10, lines: 60-5) structure facing the second semiconductor chip (Fig.7C (703) and Col.15, lines: 40-50).
11. (Original) The semiconductor package of claim 1, wherein the first encapsulant (Fig.7C (552) and Col. 13, lines: 10-25) covers a side surface of the first semiconductor chip (Fig. 7C (550) and Col.12, lines:55-65) and an opposite surface of a surface facing the first redistribution line structure (Fig.7C (520) and Col.9-10, lines: 60-5).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Chen et al (US 20200152563 A1; US 11342255 B2; US 20220278034 A1; US 11942408 B2; US 20240203856 A1; US 12500158 B2; US 20260076227 A1) teaches similar stacked devices including RDL layers/ encapsulants and bump connectors.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to LAURA M MENZ whose telephone number is (571)272-1697. The examiner can normally be reached Monday-Friday 7:00-3:30.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Steven Gauthier can be reached at 571-270-0373. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/LAURA M MENZ/Primary Examiner, Art Unit 2813
5/1/26
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