The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Claim Rejections - 35 USC § 103
1. The following is a quotation of 35 U.S.C. 103(a) which forms the basis for all obviousness rejections set forth in this Office action:
(a) A patent may not be obtained though the invention is not identically disclosed or described as set forth in section 102 of this title, if the differences between the subject matter sought to be patented and the prior art are such that the subject matter as a whole would have been obvious at the time the invention was made to a person having ordinary skill in the art to which said subject matter pertains. Patentability shall not be negatived by the manner in which the invention was made.
2. Claim 1-18 rejected under 35 U.S.C. 103(a) as being unpatentable over Izumi et al. (U.S. Patent Application Publication 2016/0093524, hereinafter referred to as Izumi) in view of SHARANGPANI et al. (U.S. Patent Application Publication 2020/0152655, hereinafter referred to as SHARANGPANI).
As to claim 1, Izumi teaches 1. A semiconductor device, comprising: a substrate having a cell array region and a contact region; the cell array region including a gate stack structure having a plurality of interlayer insulation layers and a plurality of gate electrodes alternately stacked on the substrate; the contact region including a gate pattern stack structure having a plurality of gate patterns and a plurality of insulation layers alternately stacked on the substrate, the plurality of gate patterns extending from and integral with the plurality of gate electrodes, the contact region further including a gate contact portion penetrating at least a portion of the gate pattern stack structure and electrically connected to the gate pattern; and a channel structure penetrating the gate stack structure and extending in a direction intersecting the substrate. [see 100, 300, 32, 42, 55 in Fig. 1~16]
Izumi may not explicitly teach the plurality of insulation layers including a first insulation layer and a second insulation layer, the second insulation layer being made of a material different than the first insulation layer.
SHARANGPANI teaches this limitation [see 32, 32, 45 in Fig.2; ¶0039 for example]
Therefore, it would have been obvious to one of ordinary skill in the art at the time the invention was made to combine the teachings of Izumi and SHARANGPANI to “use a first insulation layer and a second insulation layer" in Izumi according to SHARANGPANI, for the further advantage of “utilizing known method of obtaining etch selectivity”. […Referring to FIGS. 8A and 8B, an etchant that selectively etches the sacrificial material of the sacrificial material layers 42 with respect to the materials of the insulating layers 32 and the nucleation promoter layers 45 can be introduced into the backside trenches 79, for example, using an etch process….¶0085]
As to claim 2, Izumi and SHARANGPANI teaches 2. The semiconductor device as claimed in claim 1, wherein the gate contact portion: penetrates a through-gate pattern that is at least a portion of the plurality of gate patterns and is insulated from the through-gate pattern by a gate spacer; and connects to a connection gate electrode in a lower portion of the penetration gate pattern. [Izumi Fig. 16]
As to claim 3, Izumi and SHARANGPANI teaches 3. The semiconductor device as claimed in claim 2, wherein a lower surface of the gate contact portion is aligned on a same boundary as a lower surface of the gate spacer, or protrudes further toward the substrate beyond the lower surface of the gate spacer. [Izumi Fig. 16]
As to claim 4, Izumi and SHARANGPANI teaches 4. The semiconductor device as claimed in claim 1, wherein a side surface of the gate pattern stack structure is aligned in a direction perpendicular to the substrate. [Izumi Fig. 16]
As to claim 5, Izumi and SHARANGPANI teaches 5. The semiconductor device as claimed in claim 1, wherein the second insulation layer includes at least one element or isotope not contained in the first insulation layer and an organic polymer. [SHARANGPANI ¶0039]
As to claim 6, Izumi and SHARANGPANI teaches 6. The semiconductor device as claimed in claim 5, wherein the second insulation layer includes at least one of carbon, boron, fluorine, potassium, gold, platinum, calcium, and titanium. [SHARANGPANI ¶0039]
As to claim 7, Izumi and SHARANGPANI teaches 7. The semiconductor device as claimed in claim 6, wherein: the first insulation layer includes silicon oxide; and the second insulation layer includes at least one of silicon carbonate, silicon carbonate nitride, and silicon carbonitride. [SHARANGPANI ¶0039]
As to claim 8, Izumi and SHARANGPANI teaches 8. The semiconductor device as claimed in claim 5, wherein the second insulation layer includes a metal compound having a metal different from the gate pattern or a compound doped with the metal. [SHARANGPANI ¶0039]
As to claim 9, Izumi and SHARANGPANI teaches 9. The semiconductor device as claimed in claim 1, wherein the second insulation layer has an etch selectivity with respect to the first insulation layer. [SHARANGPANI ¶0039]
As to claim 10, Izumi and SHARANGPANI teaches 10. The semiconductor device as claimed in claim 1, wherein the second insulation layer has a lower dielectric constant than the first insulation layer or silicon oxide. [SHARANGPANI ¶0039]
As to claim 11, Izumi and SHARANGPANI teaches 11. The semiconductor device as claimed in claim 1, wherein a thickness of the second insulation layer is less than a thickness of the first insulation layer. [SHARANGPANI ¶0039]
As to claim 12, Izumi and SHARANGPANI teaches 12. The semiconductor device as claimed in claim 11, wherein the thickness of the second insulation layer is 1/100 to 1/10 of a thickness of the interlayer insulation layer. [SHARANGPANI ¶0039]
As to claim 13, Izumi and SHARANGPANI teaches 13. The semiconductor device as claimed in claim 1, wherein the gate pattern is formed as same layers as the gate electrode is formed. [Izumi Fig. 16]
As to claim 14, Izumi and SHARANGPANI teaches 14. The semiconductor device as claimed in claim 1, wherein: each of the interlayer insulation layers includes a first interlayer insulation layer and a second interlayer insulation layer positioned on the gate electrode; and the second insulation layer and the second interlayer insulation layer are formed as a same layer, and the first insulation layer and the first interlayer insulation layer are formed as a same layer. [SHARANGPANI Fig. 15]
As to claim 15, Izumi and SHARANGPANI teaches 15. An electronic system, comprising: a main substrate; a semiconductor device on the main substrate; and a controller electrically connected to the semiconductor device on the main substrate, the semiconductor device having a circuit region including a peripheral circuit structure and a cell region on the circuit region and including a cell array region and a contact region, the cell region having: a gate stack structure in the cell array region, including a plurality of interlayer insulation layers and a plurality of gate electrodes alternately stacked on the substrate; a gate pattern stack structure in the contact region, including a plurality of gate patterns and a plurality of insulation layers alternately stacked, the plurality of gate patterns extending from and integral with the plurality of gate electrodes, the plurality of insulation layers including at least one first insulation layer and at least one second insulation layer, the second insulation layer being made of a material different than the first insulation layer, the contact region further including a gate contact portion penetrating at least a portion of the gate pattern stack structure and electrically connected to the gate pattern; and a channel structure penetrating the gate stack structure to extend in a direction intersecting the substrate. [Izumi Fig. 1~16; SHARANGPANI Fig.2, ¶0039]
As to claim 16, Izumi and SHARANGPANI teaches 16. The electronic system as claimed in claim 15, wherein the second insulation layer includes at least one element or isotope not contained in the first insulation layer and an organic polymer. [SHARANGPANI ¶0039]
As to claim 17, Izumi and SHARANGPANI teaches 17. The electronic system as claimed in claim 15, further comprising a gate spacer surrounding the gate contact portion, wherein a lower surface of the gate contact portion is aligned on a same boundary as a lower surface of the gate spacer, or protrudes further toward the substrate beyond the lower surface of the gate spacer. [SHARANGPANI ¶0039]
As to claim 18, Izumi and SHARANGPANI teaches 18. The electronic system as claimed in claim 17, wherein a side surface of the gate pattern stack structure is aligned in a direction perpendicular to the substrate.
Conclusion
Claims 1-18 are rejected as explained above.
The prior art made of record in the PTO-892 form and not relied upon is considered pertinent to applicant's disclosure.
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/JAEHWAN OH/
Primary Examiner, Art Unit 2899
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