Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
Claims 1-3 and 5 are rejected under 35 U.S.C. 103 as being unpatentable over Kim et al. (US 7,514,310, hereinafter Kim).
With respect to claim 1, Kim discloses a gate structure (Fig. 5D), comprising:
a first conductive pattern (108) including a first metal (Col. 8; lines 45-46 – metal layer) or a first metal compound;
a second conductive pattern (116) on the first conductive pattern, the second
conductive pattern including a third metal (Col. 9; lines 20-25; 116 may comprise of metal); and
a gate insulation pattern (106 & 118) covering a lower surface and a sidewall of the first
conductive pattern (106 &118 covers lower surface and sidewall of 108) and a sidewall of the second conductive pattern (106 & 118 covers sidewall of 116).
Kim in the same embodiment does not explicitly disclose that the first conductive pattern being doped with a second metal or silicon; and wherein a work function of the second metal is smaller than a work function of the first metal and is smaller than a work function of the first metal compound.
In another embodiment Kim discloses that the first conductive pattern being doped with a second metal or (Col. 5; line 65-Col. 6, line 7 – Aluminum doping); and wherein a work function of the second metal is smaller than a work function of the first metal and is smaller than a work function of the first metal compound (Col. 6; lines 1-7; aluminum is added for reducing the work function of the metal layer).
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify Kim’s first embodiment by having disclosure from second embodiment in order to control the gate resistance to reduce signal delays and power losses.
With respect to claim 2, Kim discloses wherein the first metal includes
tantalum (Ta) (Col. 8; lines 55-58 & Col. 9; lines 55-57 -tantalum).
With respect to claim 3, Kim discloses wherein the first metal
compound includes La₂O₃, Sc₂O₃, Al₂O₃, MgO, HfO₂, Y₂O₃, LaN, TaN, TiN, TiSiN,
TiAIN, AIN, or TiAlC (Col. 8; lines 55-57; TaN)
With respect to claim 5, Kim discloses wherein the third metal includes molybdenum (Mo), ruthenium (Ru), copper (Cu), iridium (Ir), or rhodium (Rh) (Col. 2, lines 25-30 & Col. 8, lines 51-57 – Mo, Ru).
Claims 4 is rejected under 35 U.S.C. 103 as being unpatentable over Kim in view of Joo (DE 102005058139, hereinafter Joo).
With respect to claim 4, Kim does not explicitly disclose wherein: the first conductive pattern is doped with the second metal, and the second metal includes lanthanum (La), scandium (Sc), or hafnium (Hf).
In an analogous art, Joo discloses wherein: the first conductive pattern is doped with the second metal (Page 05; Para 01), and the second metal includes lanthanum (La), scandium (Sc), or hafnium (Hf) (Page 05; Para 01- doping metal layer with hafnium).
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify Kim’s device by having Joo’s disclosure in order to control the gate resistance to reduce signal delays and power losses.
Claims 6 and 8 are rejected under 35 U.S.C. 103 as being unpatentable over Kim in view of Mo et al. (US 2011/0156158, hereinafter Mo).
With respect to claim 6, Kim does not explicitly disclose a third conductive pattern on the second conductive pattern, wherein the third conductive pattern includes polysilicon doped with impurities.
In an analogous art, Mo discloses a third conductive pattern on the second conductive pattern (90 of Fig. 14), wherein the third conductive pattern includes polysilicon doped with impurities (Para 0072 – doped layer 90). Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify Kim’s device by having Joo’s disclosure in order to increase the electrical conductivity of a semiconductor device.
With respect to claim 8, Kim discloses a gate mask on the third conductive pattern (Col. 9; lines 7-10 & Col. 10; lines 36-45; mask layer is formed on the top of the gate stack), wherein the gate insulation pattern covers a sidewall of the gate mask (Col. 9; lines 35-40 – spacers are formed on sidewall of the stacked structure).
Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over Kim/Mo in view of Hoffmann et al. (US 9,281,248, hereinafter Hoffmann).
With respect to claim 7, Kim/Mo does not explicitly disclose a barrier pattern between the second conductive pattern and the third conductive pattern.
In an analogous art, Hoffmann discloses a barrier pattern between the second conductive pattern and the third conductive pattern (Fig. 1f-1j – layer between La cap & poly deposition).
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify Kim/Mo’s device by having Joo’s disclosure in order to improve device performance by reducing leakage.
Claims 9 and 11-13 are rejected under 35 U.S.C. 103 as being unpatentable over Mo in view of Kim.
With respect to claim 9, Mo discloses a gate structure (Fig. 13), comprising:
a first conductive pattern (75) including a first metal compound (Para 0065 – oxide or nitrides of metals); a second conductive pattern (85) on the first conductive pattern (Fig. 13), the second conductive pattern including a second metal (Para 0070 – Ti or Ta); a third conductive pattern (90) on the second conductive pattern (Para 0072), the third conductive pattern being doped (Para 0072 – doped gate electrode 90) and including a third metal or a second metal compound (Para 0072).
Mo does not explicitly disclose that the first conductive pattern being doped with a first metal or silicon; wherein a work function of the first metal is smaller than a work function of the first metal compound; and the third conductive pattern being doped with a fourth metal.
In an analogous art, Kim discloses that the first conductive pattern being doped with a first metal or silicon (Col. 5; line 65-Col. 6, line 7 – Aluminum doping); wherein a work function of the first metal is smaller than a work function of the first metal compound (Col. 6; lines 1-7; aluminum is added for reducing the work function of the metal layer) and the third conductive pattern being doped with a fourth metal (Col. 5; lines 45-60 and Col. 6; lines 1-3; doping with cerium ).
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify Mo’s device by having Kim’s disclosure in order to control the gate resistance to reduce signal delays and power losses.
With respect to claim 11, Mo discloses wherein the first metal
compound includes La₂O₃, Sc₂O₃, Al₂O₃, MgO, HfO₂, Y₂O₃, LaN, TaN, TiN, TiSiN,
TiAIN, AIN, or TiAlC (Para 0065 – MgO; La2O3).
With respect to claim 12, Mo does not explicitly disclose wherein the second metal includes molybdenum (Mo), ruthenium (Ru), copper (Cu), iridium (Ir), or rhodium (Rh).
In an analogous art, Kim discloses wherein the second metal includes molybdenum (Mo), ruthenium (Ru), copper (Cu), iridium (Ir), or rhodium (Rh) (Col. 2; lines 25-30 – Mo, Ru, etc.).
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify Mo’s device by having Kim’s disclosure in order to control the gate resistance to reduce signal delays and power losses.
With respect to claim 13, Mo does not explicitly disclose wherein: the third conductive pattern includes the third metal, and the third metal includes molybdenum (Mo).
In an analogous art, Kim discloses wherein: the third conductive pattern includes the third metal, and the third metal includes molybdenum (Mo) (Col. 2; lines 25-30 – Mo).
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify Mo’s device by having Kim’s disclosure in order to control the gate resistance to reduce signal delays and power losses.
Claims 10 and 15 are rejected under 35 U.S.C. 103 as being unpatentable over Kim/Mo in view of Joo.
With respect to claim 10, Kim/Mo does not explicitly disclose wherein: the first conductive pattern is doped with the first metal, and the first metal includes lanthanum (La), scandium (Sc), or hafnium (Hf).
In an analogous art, Joo discloses wherein: the first conductive pattern is doped with the first metal (Page 05; Para 01), and the first metal includes lanthanum (La), scandium (Sc), or hafnium (Hf) (Page 05; Para 01- doping metal layer with hafnium).
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify Kim/Mo’s device by having Joo’s disclosure in order to control the gate resistance to reduce signal delays and power losses.
With respect to claim 15, Kim/Mo does not explicitly disclose wherein the fourth metal includes lanthanum (La), scandium (Sc), hafnium (Hf), or tantalum (Ta).
In an analogous art, Joo discloses wherein: wherein the fourth metal includes lanthanum (La), scandium (Sc), hafnium (Hf), or tantalum (Ta) (Page 05; Para 01- doping metal layer with hafnium).
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify Kim/Mo’s device by having Joo’s disclosure in order to control the gate resistance to reduce signal delays and power losses.
Claims 14 is rejected under 35 U.S.C. 103 as being unpatentable over Kim/Mo in view of Hoffmann.
Regarding claim 14, Kim/Mo does not explicitly disclose wherein: the third conductive pattern includes the second metal compound, and the second metal compound includes TiN, TiSiN, TiAIN, or TiAlC.
In an analogous art, Hoffmann discloses wherein: the third conductive pattern includes the second metal compound, and the second metal compound includes TiN, TiSiN, TiAIN, or TiAlC (Col. 4; lines 15-20 ; Fig. 1f-I – TiN).
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify Kim/Mo’s device by having Hoffmann’s disclosure in order to reduce device failures.
Allowable Subject Matter
Claims 16-20 have been allowed.
With respect to claim 16, none of the prior art on record disclose or render obvious the claimed limitations including “a bit line structure on a central portion of the active pattern, the bit line structure extending in a second direction substantially parallel to the upper surface of the substrate; a contact plug structure contacting each opposite end portions of the active pattern; and a capacitor structure on the contact plug structure; wherein: the gate structure includes: a first conductive pattern including a first metal compound, the first conductive pattern being doped with a first metal or silicon, a second conductive pattern on the first conductive pattern, the second conductive pattern including a second metal, a third conductive pattern on the second conductive pattern, a gate mask on the third conductive pattern, and a gate insulation pattern covering a lower surface and a sidewall of the first conductive pattern, a sidewall of the second conductive pattern, and a sidewall of the third conductive pattern, and a work function of the first metal is smaller than a work function of the first metal compound” when considered as a whole along with all of the limitations of the base claim and any intervening claims.
Claims 17-20 have been allowed because of their dependency on claim 16.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MOHAMMAD M CHOUDHRY whose telephone number is (571)270-5716. The examiner can normally be reached Monday - Friday.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Zandra Smith can be reached at 571-272-2429. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/MOHAMMAD M CHOUDHRY/Primary Examiner, Art Unit 2899