DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 1, 2, 5, 7 – 11 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chung, US 5,094,981 in view of Paek, US 6,774,023.
Regarding Claim 1, Chung teaches a method of forming a semiconductor structure, the method comprising: the substrate comprising an n transistor and the p transistor and having a first opening over the n transistor and a second opening over the p transistor (Fig. 1a – 1e); optionally, in-situ annealing the substrate in an atmosphere of hydrogen (H2) (column 5, lines 10 – 20); forming a titanium silicide (TiSi) layer 34 on the n transistor and on the p transistor; and forming a capping layer (TiN in column 8, lines 41 – 45) on the titanium silicide (TiSi) layer with references to Figs. 1 and 2 in columns 3 – 7.
Chung fails to teach depositing a molybdenum silicide (MoSi) layer on one or more of a p transistor and an n transistor of a substrate.
Paek teaches a method of forming contacts with dual layer silicides wherein he first deposits a molybdenum silicide (MoSi) layer and then a titanium silicide (TiSi) layer with reference to Figs. 2 and 3 in column 4, lines 55 – 65 for the benefit of preventing the high temperature instability of the TiSi layer in column 2, lines12 – 18.
Therefore, it would have been obvious to one with ordinary skill in the art before the effective filing date of the claimed invention to modify Chung and deposit a molybdenum silicide (MoSi) layer on one or more of a p transistor and an n transistor of a substrate before forming the TiSi layer for the benefit of preventing the high temperature instability of the TiSi layer as taught by Paek in column 2, lines12 – 18.
Regarding Claim 2, Chung teaches depositing a gap fill material 40 independently in the first opening and in the second opening with reference to Figs. 1e and 2d in column 5, lines 57 – 65.
Regarding Claim 5, Chung teaches wherein the capping layer comprises one or more of tungsten (W), molybdenum (Mo), ruthenium (Ru), titanium nitride (TiN), tantalum nitride (TaN), and tungsten nitride (WN), (TiN in column 8, lines 41 – 45).
Regarding Claim 7, Chung in view of Paek, fails to teach wherein the gap fill material is substantially free of voids or seams.
However, it would have been obvious to one with ordinary skill in the art before the effective filing date of the claimed invention to modify Chung in view of Paek to have the gap fill material substantially free of voids or seams for the benefit of maintaining the low contact resistance of the fill material.
Regarding Claim 8, Chung teaches wherein the gap fill material comprises one or more of tungsten (W), molybdenum (Mo), cobalt (Co), and ruthenium (Ru) in column 7, lines 53 – 57.
Regarding Claims 9 and 10, Paek teaches wherein the method results in a contact resistance that is lower than a contact resistance of a p transistor or an n transistor comprising molybdenum silicide or the titanium silicide alone in between column 4, line33 and column 5, line 10 with reference to Fig. 4. It would have been obvious to one with ordinary skill in the art before the effective filing date of the claimed invention the sheet resistance correlates directly with the contact resistance for the transistor.
Regarding Claim 11, Chung in view of Paek teaches wherein the molybdenum silicide (MoSi) layer is on both the n transistor and on the p transistor since the dual layers are deposited on both sides.
Claim(s) 3 and 4 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chung, US 5,094,981 in view of Paek, US 6,774,023 as applied to claim 1 above, and further in view of Iwata, US 5,849,634.
Chung in view of Paek teaches silicide formation, but fails to teach method further comprising pre-cleaning the substrate and wherein the method is an integrated method performed in a cluster tool.
Iwata teaches a method for forming low resistive silicide with various steps of pre-cleaning the substrate of removing oxide and using the cluster tool with reference to Example 1 in column 7 for the benefit of producing a silicide film for semiconductor device with low sheet resistance in column 4, lines 14 – 24.
Therefore, it would have been obvious to one with ordinary skill in the art before the effective filing date of the claimed invention to modify Chung in view of Paek to pre-clean the substrate and wherein the method is an integrated method performed in a cluster tool for the benefit of producing a silicide film for semiconductor device with low sheet resistance as taught by Iwata in column 4, lines 14 – 24.
Claim(s) 6 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chung, US 5,094,981 in view of Paek, US 6,774,023 as applied to claim 1 above, and further in view of Xiang, US 6,600,170.
Chung in view of Paek teaches a MOSFET device, but fails to teach
wherein the n transistor comprises silicon (Si) doped with phosphorous (P), and the p transistor comprises silicon germanium (SiGe) doped with boron (B).
Xiang teaches a transistor wherein the n transistor comprises silicon (Si) doped with phosphorous (P), and the p transistor comprises silicon germanium (SiGe) doped with boron (B) with references to Figs. 1 – 6 in columns 3 – 5 for the benefit of providing a semiconductor device art to provide CMOS transistors, which combine more closely balanced PMOS and NMOS transistors with the increased speed of strained silicon, provide smaller devices and combine higher speed and smaller device-size to provide a more balanced CMOS transistor in column 2, lines 10 – 16.
Therefore, it would have been obvious to one with ordinary skill in the art before the effective filing date of the claimed invention to modify Chung in view of Paek to provide the n transistor comprising silicon (Si) doped with phosphorous (P), and the p transistor comprising silicon germanium (SiGe) doped with boron (B) for the benefit of providing a semiconductor device art to provide CMOS transistors, which combine more closely balanced PMOS and NMOS transistors with the increased speed of strained silicon, provide smaller devices and combine higher speed and smaller device-size to provide a more balanced CMOS transistor as taught by Xiang in column 2, lines 10 – 16.
Regarding Claims 12 and 19, the limitations have been described earlier in rejecting Claims 1 and 2.
Regarding Claim 13, the limitations have been described earlier in rejecting Claim 5.
Regarding Claim 14, the limitations have been described earlier in rejecting Claim 8.
Regarding Claim 15, the limitations have been described earlier in rejecting Claim 6.
Regarding Claim 16, the limitations have been described earlier in rejecting Claim 7.
Regarding Claim 17, the limitations have been described earlier in rejecting Claim 9.
Regarding Claim 18, the limitations have been described earlier in rejecting Claim 10.
Regarding Claim 20, the limitations have been described earlier in rejecting Claim 11.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ASOK K SARKAR whose telephone number is (571)272-1970. The examiner can normally be reached Mon - Fri; 9:30 AM - 6:30 PM.
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/ASOK K SARKAR/Primary Examiner, Art Unit 2891 February 15, 2026
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