DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Status of Application
In response to Office action dated 04/08/2026 (“04-08-26 OA”), Applicant filed remarks and currently amended title and claims 1-6, 8-20 and 22-25 in reply dated 06/29/2026 (“06-29-26 Reply”).
Response to Arguments
Applicant’s amendments to title have overcome the objection to specification as set forth under line item number 1 of the 04-08-26 OA.
Applicant’s amendments to the independent claims 1, 16 and 22 overcome the 35 USC 112(a) written description rejections of claim 1-25 as set forth under line item number 2 of the 04-08-26 OA.
Applicant’s amendments to independent claims 1, 16 and 22 and dependent claims 9 and 12 overcome the 35 USC 112(b) indefiniteness rejections of claims 1-25 as set forth under line item number 3 of the 04-08-26 OA.
Applicant’s amendments to independent claims 1, 16 and 22 overcome the prior art rejections based at least in part on Fulford as set forth under line item numbers 4-5 of the 04-08-26 OA.
Applicant’s amendments to independent claims 1, 16 and 22 overcome the prior art rejections based at least in part on Peng as set forth under line item number 6 of the 04-08-26 OA.
Applicant’s amendments to independent claims 1, 16 and 22 overcome the prior art rejections based at least in part on Chang as set forth under line item number 7 of the 04-08-26 OA.
Applicant’s amendments to independent claims 1, 16 and 22 overcome the prior art rejections based at least in part on Hong as set forth under line item number 8 of the 04-08-26 OA.
Claim Interpretation
The limitation “the first nanosheet structure and the second nanosheet structure each include one of a p-type epitaxial layer, an n-type epitaxial layer, and a gap fill layer” requires that each individual nanosheet structure include at least one of a p-type epitaxial layer, an n-type epitaxial layer, or a gap fill layer. The limitation does not require that all three features be present in the same nanosheet structure.
The second “wherein” clause of claim 1 compares the combination of those features in the first stacked nanosheet structure as a whole (its first-level nanosheet structure together with its second-level nanosheet structure) with the combination of those features in the second stacked nanosheet structure as a whole.
The same interpretation applies to the corresponding language of claims 16 and 22.
Claim Objections
Independent claims 1 and 16 are objected to because of the following informalities: first sentence last “wherein” clause recites singular epitaxial layer and gap fill layer, however Office believes these should be plural as illustrated in independent claim 22 of the first sentence last “wherein” clause. Appropriate correction is required.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1–3, 5, 8, 10, 13, 16–20, and 22–23 are rejected under 35 U.S.C. § 102(a)(1) as being anticipated by Xie et al. (US 2023/0085628 A1) (“Xie”).
Xie published on March 23, 2023, and is prior art under 35 U.S.C. § 102(a)(1) as of that date.
Regarding independent claim 1, Xie teaches:
A semiconductor device comprising:
IC 200 (“integrated circuit”; FIG. 20: an IC including different types of hybrid stacked semiconductor devices).
a first stacked nanosheet structure
60 (“stacked CMOS FET”; FIG. 1: an NFET stacked over a PFET, or vice versa, formed as a top nanosheet stack on a bottom nanosheet stack).
and a second stacked nanosheet structure
10 (“pair of stacked NFETs”; FIG. 1: two n-type nanosheet FETs stacked at two levels). Both 60 and 10 are present on the same device in 200 (FIG. 20: “The IC 200 includes a collection of hybrid stacked semiconductor devices 10 that include a pair of stacked NFETs … along with a collection of hybrid stacked semiconductor device 60 that include a stacked CMOS FET”).
each including a first nanosheet structure formed at a first level
115 (“bottom NS stack” / “first stack portion”; FIGS. 2–19: the lower nanosheet stack portion on the substrate).
and a second nanosheet structure formed at a second level,
113 (“top NS stack” / “second stack portion”; FIGS. 2–19: the upper nanosheet stack portion stacked on 115).
wherein for each of the first stacked nanosheet structure and the second stacked nanosheet structure, the first nanosheet structure and the second nanosheet structure each include one of a p-type epitaxial layer, an n-type epitaxial layer, and a gap fill layer, and
132 (“first source/drain”; FIG. 11: bottom S/D contacting 115) and 134 (“second source/drain”; FIG. 11: top S/D contacting 113) are n-type or p-type epitaxial source/drain regions depending on device polarity. In 60, one of 132 and 134 is n-type epitaxy and the other is p-type epitaxy (FIG. 1: NFET stacked over PFET, or vice versa). In 10, both 132 and 134 are n-type epitaxy (FIG. 1: pair of stacked NFETs). 202 (“dielectric spacer”; FIG. 9: dielectric replacing sacrificial spacer layer 112 and separating 113 from 115) is a gap fill layer between the two levels.
wherein a combination of the epitaxial layer and the gap fill layer for the first stacked nanosheet structure is different than a combination of the epitaxial layers and the gap fill layers for the second stacked nanosheet structure.
On 200, the combination for 60 is n-type epitaxy and p-type epitaxy. The combination for 10 is n-type epitaxy and n-type epitaxy. Those combinations are different (FIG. 20).
Regarding claim 2, Xie teaches the limitations of at least one of the respective first nanosheet structures and the second nanosheet structures being a FET that includes a nanosheet stack in contact with one of the p-type epitaxial layers or one of the n-type epitaxial layers. 132 contacts the channels of 115 and 134 contacts the channels of 113 (FIG. 11). 132 and 134 are n-type or p-type epitaxial source/drain regions as required by the polarity of 10 and 60 (FIG. 1).
Regarding claim 3, Xie teaches the first nanosheet structure of the first stacked nanosheet structure including one of the p-type epitaxial layers, the first nanosheet structure of the second stacked nanosheet structure including one of the n-type epitaxial layers, the first nanosheet structure of the first stacked nanosheet structure including alternating layers of a semiconductor layer and a p-type work function metal (WFM) layer, and the first nanosheet structure of the second stacked nanosheet structure including alternating layers of the semiconductor layer and an n-type work function metal (WFM) layer. On 200, 60 may have a PFET at the first level (bottom 115) so that 132 is p-type epitaxy, while 10 has n-type epitaxy at the first level so that 132 of 10 is n-type epitaxy (FIG. 1: “an NFET stacked over a PFET, and vice versa”).
144 (“all-around gate”; FIG. 14: high-k metal gate wrapping semiconductor layers 108 of 113 and 115) includes a work-function metal layer. Xie teaches that the high-k metal gate material includes a high-k dielectric layer and a work-function metal (WFM) layer, and that 144 includes one or more work function layers between the high-k dielectric and the bulk gate material. The WFM is the polarity of the device being gated. Channel layers 108 alternate with the gate/WFM wrap in the GAA structure.
Regarding claim 5, Xie teaches n-type epitaxy on the second level of the first stacked structure, p-type epitaxy on the first level of the first stacked structure, and n-type epitaxy on both levels of the second stacked structure. This is 200: 60 with PFET at 115 and NFET at 113 (FIG. 1, vice versa expressly taught), and 10 with n-type epitaxy at both 115 and 113.
Regarding claim 8, Xie teaches that the n-type epitaxial layer and the p-type epitaxial layer of the first stacked nanosheet structure do not directly contact each other, and that the two n-type epitaxial layers of the second stacked nanosheet structure do not directly contact each other. 202 separates 113 from 115 (FIG. 9). 132 contacts only 115 and 134 contacts only 113 (FIG. 11). The two epitaxial regions therefore do not directly contact each other in 60 or in 10.
Regarding claim 10, Xie teaches that the first stacked nanosheet structure is a stacked CMOS device where the first nanosheet structure includes the n-type epitaxial layer and the second nanosheet structure includes the p-type epitaxial layer. 60 is a stacked CMOS FET (FIG. 1). Xie teaches an NFET stacked over a PFET and vice versa. First-level n-type epitaxy at 115 with second-level p-type epitaxy at 113 is therefore taught.
Regarding claim 13, Xie teaches same-type epitaxy on both levels of the first stacked nanosheet structure, separation of those epitaxial layers, and separate metal contacts. Mapping the first stacked structure to 10 (or to 20 (“pair of stacked PFETs”; FIG. 1)), both levels have the same type of epitaxy. 202 separates 132 from 134 (FIGS. 9 and 11). 10 has independently controlled gates with 146 (“first gate contact”; FIG. 14) and 148 (“second gate contact”; FIG. 14), and separate source/drain contacts.
Regarding independent claim 16, Xie teaches an electronic device comprising a semiconductor device that includes a first stacked nanosheet structure and a second stacked nanosheet structure with the same limitations mapped for claim 1. 200 is an electronic device (FIG. 20: for example a local register file in an AI hardware accelerator) that includes 60 and 10 with different epitaxy combinations.
Regarding claim 17, Xie teaches the FET including a nanosheet stack in contact with one of the p-type epitaxial layers or one of the n-type epitaxial layers. 132 contacts 115 and 134 contacts 113 (FIG. 11).
Regarding claim 18, Xie teaches the first-level p-type epitaxy / n-type epitaxy and corresponding p-type WFM / n-type WFM limitations. On 200, 60 may have p-type epitaxy at 115 and 10 has n-type epitaxy at 115 (FIG. 1). 144 includes a WFM layer of the polarity of the gated device (FIG. 14).
Regarding claim 19, Xie teaches p-type epitaxy on the second nanosheet structure of the first stacked structure and n-type epitaxy on the first nanosheet structure of the second stacked structure. On 200, 60 may have p-type epitaxy at 113, and 10 has n-type epitaxy at 115 (FIG. 1).
Regarding claim 20, Xie teaches n-type epitaxy on the second level of the first stacked structure, p-type epitaxy on the first level of the first stacked structure, and n-type epitaxy on both levels of the second stacked structure. This is 200: 60 with p-type at 115 and n-type at 113, and 10 with n-type at both levels.
Regarding independent claim 22, Xie teaches a semiconductor device comprising a first stacked nanosheet structure and a second stacked nanosheet structure, each including a first nanosheet structure at a first level and a second nanosheet structure at a second level and at least one epitaxial layer, wherein for each stacked structure the first and second nanosheet structures each include one of a p-type epitaxial layer, an n-type epitaxial layer, and a gap fill layer, and wherein the combination of those features for the first stacked nanosheet structure is different from the combination for the second stacked nanosheet structure. 200 includes 60 and 10, each a two-level stack (113 over 115) with epitaxial source/drain 132, 134 and dielectric 202, with different combinations as mapped for claim 1.
Regarding claim 23, Xie teaches p-type epitaxy on the second nanosheet structure of the first stacked structure and n-type epitaxy on the first nanosheet structure of the second stacked structure. On 200, 60 may have p-type epitaxy at 113, and 10 has n-type epitaxy at 115 (FIG. 1).
Allowable Subject Matter
Claims 4, 6, 7, 9, 11, 12, 14, 15, 21, 24, and 25 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Regarding claim 4, Xie does not teach same-type epitaxy on both levels of the first stacked nanosheet structure with those epitaxial layers in direct contact with each other. Xie teaches 10 and 20, which have the same polarity on both levels, but 132 on 115 is isolated from 134 on 113 by 202 (FIGS. 9 and 11). Direct contact of the two epitaxial layers is required by claim 4 and is not present in Xie. Claim 4 is therefore allowable over Xie.
Regarding claim 6, Xie does not teach opposite-type epitaxy on the two levels of the first stacked nanosheet structure with those epitaxial layers in direct contact with each other. 60 has opposite polarity on the two levels, but 202 isolates 132 from 134 so the n-type epitaxy and the p-type epitaxy do not touch (FIGS. 9 and 11). Direct contact is required by claim 6 and is not present in Xie. Claim 6 is therefore allowable over Xie.
Regarding claim 7, Xie does not teach opposite-type epitaxial layers that directly contact each other and share a single metal contact. Because 202 keeps 132 and 134 apart, Xie has no merged epitaxial body to which a single shared contact could land. Separate contacts to isolated source/drain regions are not the shared contact of claim 7. Claim 7 is therefore allowable over Xie.
Regarding claim 9, Xie does not teach a third stacked nanosheet structure whose combination of p-type epitaxy, n-type epitaxy, and gap fill is different from both the first stacked nanosheet structure and the second stacked nanosheet structure. 200 places only two combinations on one device: 60 (n-type and p-type) and 10 (n-type and n-type) (FIG. 20). 20 and 40 are a third combination (p-type and p-type), but they are taught only as separate embodiments in FIG. 1, not as a third stack on the same IC as 10 and 60. A third different combination on one device is required by claim 9 and is not present in Xie. Claim 9 is therefore allowable over Xie.
Regarding claim 11, Xie does not teach the three-combination device of claim 9 in which the second stacked structure is a stacked pFET with p-type epitaxy on both levels. 200 pairs CMOS 60 with stacked NFET 10, not with stacked PFET 20. Placing a stacked pFET on the same device as two other different combinations is not taught. Claim 11 is therefore allowable over Xie.
Regarding claim 12, Xie does not teach the three-combination device of claim 9 in which the third stacked structure is a stacked nFET with n-type epitaxy on both levels. 10 is a stacked nFET, but Xie never places that stacked nFET on the same device as two other stacks that already have different combinations from each other and from the stacked nFET. Claim 12 is therefore allowable over Xie.
Regarding claim 14, Xie does not teach, on one device, a stacked CMOS combination of p-type epitaxy at the first level and n-type epitaxy at the second level together with a stacked-pFET combination of p-type epitaxy at both levels. 200 co-integrates 60 with 10 (CMOS with stacked NFET) (FIG. 20). 20 and 40 (stacked PFET) appear only as separate embodiments in FIG. 1. CMOS plus stacked pFET on the same chip is required by claim 14 and is not present in Xie. Claim 14 is therefore allowable over Xie.
Regarding claim 15, Xie does not teach, on one device, a stacked CMOS combination of n-type epitaxy at the first level and p-type epitaxy at the second level together with a stacked-pFET combination of p-type epitaxy at both levels. 200 co-integrates 60 with stacked NFET 10, not with stacked PFET 20. Claim 15 is therefore allowable over Xie.
Regarding claim 21, Xie does not teach the n-type and p-type epitaxial layers of the first stacked structure in direct contact with each other, and the two n-type epitaxial layers of the second stacked structure in direct contact with each other. In both 60 and 10, 202 stands between 132 and 134 (FIGS. 9 and 11). Direct contact in both stacks is required by claim 21 and is not present in Xie. Claim 21 is therefore allowable over Xie.
Regarding claim 24, Xie does not teach that the first stacked nanosheet structure is a single pFET standard drive current device that includes a gap fill layer covering the first nanosheet structure at the second level. 202 isolates two active stacks 113 and 115, and both levels receive epitaxy 132 or 134 (FIGS. 9 and 11). Xie does not use gap fill to cover a second-level nanosheet structure so that that level is inactive and the stacked structure operates as a single pFET. That dummy-level gap fill is required by claim 24 and is not present in Xie. Claim 24 is therefore allowable over Xie.
Regarding claim 25, Xie does not teach that the second stacked nanosheet structure is a single nFET standard drive current device that includes a gap fill layer covering the first nanosheet structure at the second level. As with claim 24, both 113 and 115 in Xie are active and receive epitaxy. A dummy second level covered by gap fill, used to form a single nFET standard drive device next to the single pFET of claim 24, is not taught. Claim 25 is therefore allowable over Xie.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JOHN P DULKA whose telephone number is (571)270-7398. The examiner can normally be reached Monday-Friday, 9am-5pm, EST.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, ELISEO RAMOS-FELICIANO can be reached at (571)272-7925. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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11 September 2026
/John P. Dulka/Primary Examiner, Art Unit 2817
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