DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. This OA is in response to the claims filled on 12/19/2023 that has been entered, wherein claims 1-10 are pending . Drawings The drawings are objected to as failing to comply with 37 CFR 1.84(p)(5) because they do not include the following reference sign s mentioned in the description: 113 mention in ¶0015 of the as filled specification. Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance. The drawings are objected to as failing to comply with 37 CFR 1.84(p)(5) because they include the following reference character s not mentioned in the description: 107 in Figs. 1, 3-8 and 10-11. Corrected drawing sheets in compliance with 37 CFR 1.121(d), or amendment to the specification to add the reference character s in the description in compliance with 37 CFR 1.121(b) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance. Claim Rejections - 35 USC § 112 The following is a quotation of 35 U.S.C. 112(b): (b ) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. The following is a quotation of 35 U.S.C. 112 (pre-AIA), second paragraph: The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the appl icant regards as his invention. Claims 1-10 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. Claim 1 recites the limitation of “ laterally adjacent trench gates ” in line 13. How can there be laterally adjacent trench gates when claim 1, line 3 only defines a trench gate? For the purpose of examination, “a trench gate” in line 13 will be interpreted as “a trench gate comprising a plurality of trench gates” . Claim 1 recites the limitation " each contact ” in line 20. There is insufficient antecedent basis for this limitation in the claim. What does “each contact ” encompass? . line 11 or the source region source contact of line 14? For the purpose of examination, “each contact ” will be interpreted as the gate region contact , the gate region source contact and the source region source contact . Claims 2-10 depend on claim 1 and inherit it’s deficiencies. Claim 5 recites the limitation "the contact ” in line 8. There is insufficient antecedent basis for this limitation in the claim. Is the contact the gate region contact of claim 1, line 10 or the gate region source contact of claim 1, line 11 or the source region source contact of claim 1, line 14? For the purpose of examination, “the contact ” will be interpreted as the gate region contact , the gate region source contact and the source region source contact . Claims 6-9 depend on claim 5 and inherit it’s deficiencies. Claim 7 recites the limitation “ step S 1 comprises the following steps: S11, forming the N-type epitaxial layer on the N-type substrate; S12, performing P-type ion implantation in the surface layer of the N-type epitaxial layer to form the P-type bulk region; S13, performing photolithographic etching to form a gate region gate trench and a source region gate trench in the N-type epitaxial layer; S14, sequentially forming a trench gate dielectric layer and a trench gate polysilicon layer in both the gate region gate trench and the source region gate trench, so as to form the trench gate; S15, performing N-type heavy doping implantation in the surface layer of the P- type bulk region to form the source end N-type implantation region ” in lines 3-13. Claim 1, from which this claim depends Claim 7 recites the limitation “ the N-type epitaxial layer ” in line 4, “ the N-type substrate ” in line 4, “ the P-type bulk region ” in line 4, “ the source end N-type implantation region ” in line 4. There is insufficient antecedent basis for these limitations in the claim. Is the “the N-type epitaxial layer” the same or different than the “ the first -type epitaxial layer ” of claim 1, line 3 ? Is the “the N-type substrate” the same or different than the “ the first -type substrate ” of claim 1, line 3 ? Is the “ the P-type bulk region ” the same or different than the “ the second -type bulk region ” of claim 1, line 4 ? Is the “ source end N-type implantation region ” the same or different than the “ source end first -type implantation region ” of claim 1, line 6 ? For the purpose of examination, the limitation of “ The method for manufacturing a superjunction trench gate MOSFET according to claim 4, wherein ” will be interpreted as “ The method for manufacturing a superjunction trench gate MOSFET according to claim 4, wherein , the first type is an N type and the second type is a P type ”. Allowable Subject Matter Claims 1-10 would be allowable if rewritten or amended to overcome the rejections under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA), 2nd paragraph, set forth in this Office action. The following is a statement of reasons for the indication of allowable subject matter: Regarding claim 1, Shimomura (US 2023/0411512 A1) teaches a method for manufacturing a superjunction trench gate MOSFET (Figs. 1-7 and 14-17) , wherein, comprising the following steps: S1 forming a trench gate(GE, ¶0045) comprising a plurality of trench gates (GE, ¶0045) in a first-type epitaxial layer(EN, ¶0081) on an upper side of a first-type substrate(SL, ¶0081) , forming a second-type bulk region(BR, ¶0065) in a surface layer of the first-type epitaxial layer(EN, ¶0081) , and performing first-type heavy doping implantation in a surface layer of the second-type bulk region(BR, ¶0065) to form a source end first-type implantation region(SR, ¶0067) , wherein a first type is an N type (¶0045) and a second type is a P type (¶0065) , or the first type is a P type and the second type is an N type; S2, forming a first dielectric layer(IF4, ¶0045) on an upper surface of a wafer(SB, ¶0034) ; S3, covering the upper surface of the wafer(SB, ¶0034) with a first mask layer(PR4, ¶0084) , and performing etching, so as to form a gate region gate contact (CP in PER) that communicates the trench gate(GE, ¶0045) with the first dielectric layer(IF4, ¶0045) at the trench gate(GE, ¶0045) in a gate region (region of GM) , and at the same time, form a gate region source contact (CP contacting BR in the region of GM) that communicates the source end first-type implantation region(SR, ¶0067) with the second-type bulk region(BR, ¶0065) between laterally adjacent trench gates(GE, ¶0045) in the gate region (region of GM) and form a source region source contact (CP contacting BR in the region of SM) that communicates the source end first-type implantation region(SR, ¶0067) with the second-type bulk region (BR, ¶0065) between laterally adjacent trench gates(GE, ¶0045) in a source region(region of SM) ; S4, performing second-type ion implantation, so as to form a source second-type doped pillar (PC, NC ¶0085) in the first-type epitaxial layer(EN, ¶0081) below each of the gate region source contact (CP contacting BC) and the source region source contact(CP contacting BR in the region of SM) , and at the same time, form a gate second-type doped pillar (NC, ¶0085) in the first-type epitaxial layer(EN, ¶0081) below the gate region gate contact (CP contacting GE) ; S5, removing the first mask layer(PR4, ¶0084) , performing a contact metal process, and filling the gate region gate contact (CP in PER) , gate region source contact (CP contacting BR in the region of GM) and the source region source contact (CP contacting BR in the region of SM) with metal tungsten (¶0057) ; S6, performing metal layer deposition to form a top metal layer (SM, GM, ¶0058) on the upper surface of the wafer(SB, ¶0034). Shimomura does not disclose: S7, covering the top metal layer (SM, GM, ¶0058) with a second mask layer, and performing etching, so as to remove the second mask layer and the top metal layer (SM, GM, ¶0058) above the source region source contact(CP contacting BR in the region of SM) and the trench gate(GE, ¶0045) of the source region (region of SM) , retain the second mask layer and the top metal layer (SM, GM, ¶0058) above the trench gate(GE, ¶0045) of the gate region (region of GM) , and retain the second mask layer and the top metal layer (SM, GM, ¶0058) above the gate region source contact (CP contacting BR in the region of GM) ; S8, performing etching to remove the metal tungsten in the source region source contact(CP contacting BR in the region of SM) ; S9, removing the second mask layer and depositing a second dielectric layer on the upper surface of the wafer(SB, ¶0034) . Regarding independent claim 1, the prior art of record neither anticipates nor renders obvious the claimed subject matter of the instant application as a whole either taken alone or in combination, in particular, prior art of record does not teach “S7, covering the top metal layer with a second mask layer, and performing etching, so as to remove the second mask layer and the top metal layer above the source region source contact and the trench gate of the source region, retain the second mask layer and the top metal layer above the trench gate of the gate region, and retain the second mask layer and the top metal layer above the gate region source contact; S8, performing etching to remove the metal tungsten in the source region source contact; S9, removing the second mask layer and depositing a second dielectric layer on the upper surface of the wafer.” Conclusion The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Hsieh et al. (US 2021/0020776 A1) Discloses a method for manufacturing a superjunction trench gate MOSFET . Nabuchi et al. (US 2023/0112550 A1). Discloses a method for manufacturing a superjunction trench gate MOSFET . Any inquiry concerning this communication or earlier communications from the examiner should be directed to FILLIN "Examiner name" \* MERGEFORMAT LAURA DYKES whose telephone number is FILLIN "Phone number" \* MERGEFORMAT (571)270-3161 . The examiner can normally be reached FILLIN "Work Schedule?" \* MERGEFORMAT M-F 9:30 am-5 pm . Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, FILLIN "SPE Name?" \* MERGEFORMAT N. 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