DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Election/Restrictions
1. Applicant’s election without traverse of Invention I, claims 1-5, in the reply filed on 3/5/2026 is acknowledged.
Specification
2. The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
Appropriate correction is required.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
3. Claims 1-5 are rejected under 35 U.S.C. 103 as being unpatentable over Bothe et al. (US 2020/0395475) in view of Nakata et al. (US 2017/0263743).
Re claim 1, Bothe teaches, under BRI, Fig. 3, [0086, 0087, 0091-0093], a semiconductor device comprising:
-a substrate (322) having a first surface (lower surface of 322) and a second surface (upper surface of 322) opposite to the first surface;
-a first nitride semiconductor layer (324, e.g., Group II-nitride) having a third surface (lower surface) that is in contact with the second surface and a fourth surface (upper surface) opposite to the third surface;
-a second nitride semiconductor layer (326, e.g., Group III-nitride); and
-a first metal layer (315’) provided on the second nitride semiconductor layer (326),
wherein a through-hole (via 325’) is formed in the substrate (322), the first nitride semiconductor layer (324), and the second nitride semiconductor layer (326), the through-hole (325’) penetrating the substrate (322), the first nitride semiconductor layer (324), and the second nitride semiconductor layer (326) and exposing the first metal layer (315’), and
wherein the semiconductor device further comprises a second metal layer (back metal layer 335) that is in contact with the first metal layer (315’) and that covers the first surface (lower surface of 322) and an inner wall surface of the through-hole (325’).
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Bothe does not explicitly teach a recess being formed in the fourth surface; and a second nitride semiconductor layer provided in the recess, wherein the second nitride semiconductor layer contains impurity atoms at a concentration of 1.0 × 1018 cm-3 or greater.
Nakata teaches, under BRI, Fig. 6B-7, [0036], a recess (102) being formed in the fourth surface (of layer 14); and a second nitride semiconductor layer (GaN 108) provided in the recess (102), wherein the second nitride semiconductor layer (26a) contains impurity atoms at a concentration of 1.0 × 1018 cm-3 or greater (e.g., 1.0 × 1019 cm-3).
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As taught by Nakata, one of ordinary skill in the art would utilize & modify the above teaching into Bothe’s GaN-based HEMT structure to obtain a recess being formed in the fourth surface; and a second nitride semiconductor layer provided in the recess, wherein the second nitride semiconductor layer contains impurity atoms at a concentration of 1.0 × 1018 cm-3 or greater as claimed, because it aids in achieving transistor(s) with enhanced high frequency performance, increased cut-off frequency & reduced access resistance. Further, it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or working range involves only routine skill in the art. In re Alter, 105 USPQ 233.
Thus, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ the teaching as taught by Nakata in combination Bothe due to above reason.
Re claim 2, in combination cited above, Bothe teaches wherein the second nitride semiconductor (326) is a gallium nitride layer [0089] (see also Nakata, [0036]).
Re claim 3, in combination cited above, Bothe teaches, Fig. 3, [0092, 0129], wherein the first metal layer (315’) includes a nickel layer (e.g., Ni) that is in contact with the second nitride semiconductor layer and is exposed in the through-hole, and wherein the second metal layer (335) includes a gold layer (e.g., gold) that is in contact with the nickel layer.
Re claim 4, in combination cited above, Bothe/Nakata does not explicitly teach wherein a Fermi level is higher than energy at a lower end of a conduction band in the second semiconductor layer.
Nakata does teach the second semiconductor layer (108) the second nitride semiconductor layer (26a) contains impurity concentration of around 1.0 × 1019 cm-3 [0036] (similar to second nitride semiconductor layer 21S with n-type impurity) of the application).
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ/modify the teaching as taught by Nakata to achieve a Fermi level is higher than energy at a lower end of a conduction band in the second semiconductor layer as claimed, because, based on similar teaching, it aids in achieving desired properties of the formed semiconductor layer and improving the performance of the formed transistor(s).
Re claim 5, in combination cited above, Nakata teaches, [0022, 0036], wherein a carrier density (e.g. carrier (electron) concentration) in the second nitride semiconductor layer (108) is higher (e.g., based on impurity concentration in 108) than a carrier density in the first nitride semiconductor layer (14).
Double Patenting
4. The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1-5 are provisionally rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-5 of copending Application No. 19/316,280 (reference application). Although the claims at issue are not identical, they are not patentably distinct from each other because they both require and claim similar semiconductor device including a substrate, a first nitride semiconductor having recess, a second nitride semiconductor layer containing impurity atoms at a concentration of 1.0 × 1018 cm-3 or greater in the recess, a first metal layer, a through hole (vs. opening) &, gallium nitride & Fermi level, etc.
This is a provisional nonstatutory double patenting rejection because the patentably indistinct claims have not in fact been patented.
Current application 18/545,249
1. A semiconductor device comprising:
a substrate having a first surface and a second surface opposite to the first surface;
a first nitride semiconductor layer having a third surface that is in contact with the second surface and a fourth surface opposite to the third surface, a recess being formed in the fourth surface;
a second nitride semiconductor layer provided in the recess; and
a first metal layer provided on the second nitride semiconductor layer,
wherein a through-hole is formed in the substrate, the first nitride semiconductor layer, and the second nitride semiconductor layer, the through-hole penetrating the substrate, the first nitride semiconductor layer, and the second nitride semiconductor layer and exposing the first metal layer, and wherein the semiconductor device further comprises a second metal layer that is in contact with the first metal layer and that covers the first surface and an inner wall surface of the through-hole, and
wherein the second nitride semiconductor layer contains impurity atoms at a concentration of 1.0 × 1018 cm-3 or greater.
2. The semiconductor device as claimed in claim 1, wherein the second nitride semiconductor layer is a gallium nitride layer.
4. The semiconductor device as claimed in claim 1, wherein a Fermi level is higher than energy at a lower end of a conduction band in the second nitride semiconductor layer.
5. The semiconductor device as claimed in claim 1, wherein a carrier density in the second nitride semiconductor layer is higher than a carrier density in the first nitride semiconductor layer.
Copending application 19/316,280
1. A semiconductor device comprising:
a substrate having a first surface and a second surface opposite to the first surface;
a first nitride semiconductor layer having a third surface in contact with the second surface, and a fourth surface opposite to the third surface, the first nitride semiconductor layer having a recess formed in the fourth surface;
a second nitride semiconductor layer provided in the recess; and
a first metal layer,
wherein an opening is formed in the substrate and the first nitride semiconductor layer, the opening penetrating the substrate and the first nitride semiconductor layer, reaching the second nitride semiconductor layer, and having a bottom surface in the second nitride semiconductor layer, the first metal layer covers the first surface and an inner wall surface of the opening, and is in contact with the second nitride semiconductor layer at the bottom surface of the opening, and
the second nitride semiconductor layer contains impurity atoms at a concentration of 1.0 x 1018 cm-3 or higher.
3. The semiconductor device according to claim 1, wherein the second nitride semiconductor layer is
a gallium nitride layer.
4. The semiconductor device according to claim 1, wherein a Fermi level is higher than energy at a
bottom of a conduction band in the second nitride semiconductor layer.
5. The semiconductor device according to claim 1, wherein a carrier density of the second nitride semiconductor layer is higher than a carrier density of the first nitride semiconductor layer.
Conclusion
6. Any inquiry concerning this communication or earlier communications from the examiner should be directed to DUY T.V. NGUYEN whose telephone number is (571)270-7431. The examiner can normally be reached Monday-Friday, 7AM-4PM, alternative Friday off.
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/DUY T NGUYEN/Primary Examiner, Art Unit 2818 5/4/26
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