DETAILED ACTION
Election/Restrictions
Applicant’s election without traverse of Group I (claims 1-9) in the reply filed on February 5, 2026 is acknowledged.
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1 and 6 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Tsuji (US 2023/0049363 A1).
The applied reference has a common assignee with the instant application. Based upon the earlier effectively filed date of the reference, it constitutes prior art under 35 U.S.C. 102(a)(2). This rejection under 35 U.S.C. 102(a)(2) might be overcome by: (1) a showing under 37 CFR 1.130(a) that the subject matter disclosed in the reference was obtained directly or indirectly from the inventor or a joint inventor of this application and is thus not prior art in accordance with 35 U.S.C. 102(b)(2)(A); (2) a showing under 37 CFR 1.130(b) of a prior public disclosure under 35 U.S.C. 102(b)(2)(B) if the same invention is not being claimed; or (3) a statement pursuant to 35 U.S.C. 102(b)(2)(C) establishing that, not later than the effective filing date of the claimed invention, the subject matter disclosed in the reference and the claimed invention were either owned by the same person or subject to an obligation of assignment to the same person or subject to a joint research agreement.
As to claim 1, Tsuji teaches a semiconductor device comprising:
a first nitride semiconductor layer (see fig. 1; 21, 22, 23) having a first surface, and a first recess (see fig. 3) formed in the first surface;
a second nitride semiconductor layer (24, 25; see also para. 0049-0050) provided inside the first recess;
a first insulating film (51), covering the first nitride semiconductor layer and the second nitride semiconductor layer, and having a first opening exposing at least a portion of the second nitride semiconductor layer (see fig. 8); and
an interconnect layer (i.e. electrode, 41, 42) making ohmic contact with the second nitride semiconductor layer through the first opening, wherein
the second nitride semiconductor layer has a second surface opposing the interconnect layer,
a second recess (24A, 25A), continuous with the first opening, is formed in the second surface, and
the interconnect layer (41, 42) makes direct contact with the second nitride semiconductor layer at an inner surface of the second recess (as shown in figure 9).
As to claim 6, Tsuji teaches a carrier concentration in the second nitride semiconductor layer is higher than a carrier concentration in the first nitride semiconductor layer. See para. 0049.
Allowable Subject Matter
Claims 2, 5, 7, 8, and 9 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The prior art of record does not teach or suggest the disclosed invention regarding the interconnect layer including a first metal layer making direct contacting with the second nitride semiconductor layer at a side surface and a bottom surface of the second recess, and a second metal layer, laminated on the first metal layer, and having an electrical resistance lower than an electrical resistance of the first metal layer, as recited in claim 2.
The prior art of record does not teach or suggest the disclosed invention regarding a second insulating film, provided between the first nitride semiconductor layer and the first insulating film, and having a third opening exposing the first recess, as recited in claim 5.
The prior art of record does not teach or suggest the disclosed invention regarding a gate electrode provided between the first nitride semiconductor layer and the first insulating film, as recited in claim 7.
The prior art of record does not teach or suggest the disclosed invention regarding the second recess has a depth in a range greater than or equal to 5 nm and less than or equal to 50 nm, as recited in claim 8.
The prior art of record does not teach or suggest the disclosed invention regarding the first opening exposes an entirety of the second surface from the first insulating film, as recited in claim 9.
Claims 3 and 4 are also objected to as being dependent upon an objected claim.
Cited Prior Art
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure: see the attached form PTO-892 for pertinent cited art.
Contact Information
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Scott B. Geyer (telephone: 571-272-1958). The examiner can normally be reached on Monday to Friday, 10AM - 4PM (ET). Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at: http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Christine S. Kim (telephone: 571-272-8458). The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only.
For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (in U.S.A. or Canada) or 571-272-1000.
/SCOTT B GEYER/ Primary Examiner, Art Unit 2812
Prosecution Insights