DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
The 4/17/2026 "Reply" elects without traverse and identifies claims 1-3, 6, and 8-20 as being drawn to Species 1. Accordingly, Examiner has withdrawn claims 4-5 and 7 from further consideration as being drawn to a non-elected invention. See, for example, 37 CFR § 1.142(b).
The 2/18/2026 restriction requirement is proper, is maintained, and is hereby made final.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 6, and 8-10 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Yamaguchi (US Patent No. 5,398,205).
Regarding claim 1, in FIGs. 2-3 and 5-6, col. 2-col. 3, Yamaguchi discloses a semiconductor device, comprising: a substrate (10); an active pattern (1) on the substrate, wherein the active pattern includes a first edge part (left portion of 1 under 3 in FIG. 3) and a second edge part (right portion of 1 under rightmost 20 in FIG. 3) that are spaced apart from each other in a first direction (diagonal direction of 3-3 cross-section taken in FIG. 2); a word line (rightmost 2) that extends along a second direction (left-right in FIG. 2) between the first and second edge parts of the active pattern, wherein the second direction intersects the first direction; a bit line (3) that extends along a third direction (vertical direction in FIG. 2) on the first edge part of the active pattern, wherein the third direction intersects the first and second directions; a storage node contact (rightmost 20) on the second edge part of the active pattern; a first active pad (15) between the bit line and the first edge part of the active pattern; and a second active pad (14) between the storage node contact and the second edge part of the active pattern, wherein the first active pad extends in the third direction beyond the first edge part of the active pattern, and wherein the second active pad extends in a direction opposite to the third direction beyond the second edge part of the active pattern.
Regarding claim 6, in FIGs. 2-3 and 5-6, col. 2-col. 3, Yamaguchi discloses that the storage node contact (rightmost 20) partially overlaps the bit line (3) in a direction perpendicular (vertical direction in FIG. 5-6) to the second direction (left to right).
Regarding claim 8, in FIGs. 2-3 and 5-6, col. 2-col. 3, Yamaguchi discloses that the first and second active pads include a material that is same as a material of the active pattern (col. 2, lines 57-63).
Regarding claim 9, in FIG. 2, Yamaguchi discloses that the active pattern is a first active pattern, wherein the semiconductor device further comprises: a second active pattern (to the right of leftmost 1 where 3-3 cross section is taken) that is adjacent in the second direction to the first active pattern; a third active pattern (partially shown 1 below the second active pattern or adjacent portion of 1 associated with another 20 shown in FIG. 3) that is adjacent in the third direction to the second active pattern; and a fourth active pattern (partially shown 1 below the first active pattern or adjacent portion of 1 associated with the other 20 shown in FIG. 3) that is adjacent in the third direction to the first active pattern, and wherein a second edge part of the fourth active pattern, the first edge part of the first active pattern, a second edge part of the third active pattern, and a first edge part of the second active pattern are sequentially disposed along the second direction.
Regarding claim 10, in FIG. 2, Yamaguchi discloses that the word line is a first word line, wherein the semiconductor device further comprises a second word line (centermost 2 in FIG. 2) that is adjacent in the third direction to the first word line, wherein the first word line intersects the first and second active patterns, and wherein the second word line intersects the third and fourth active patterns.
Allowable Subject Matter
Claims 11-20 are allowed.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claims 11-16, the prior art failed to disclose or reasonably suggest the claimed semiconductor device particularly characterized by a top surface of the second active pad is higher than a bottom surface of the bit line with respect to the substrate.
Regarding claims 17-20, the prior art failed to disclose or reasonably suggest the claimed semiconductor device particularly characterized by a lower storage node contact on the second edge part of the active pattern; an upper storage node contact on the lower storage node contact, wherein the upper storage node contact partially overlaps the lower storage node contact in a direction perpendicular to the second direction; a second active pad between the lower storage node contact and the second edge part of the active pattern; a landing pad on the upper storage node contact; and a data storage pattern on the landing pad, wherein the second active pad extends in a direction opposite to the third direction beyond the second edge part of the active pattern.
Claims 2-3 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to TUCKER J WRIGHT whose telephone number is (571)270-3234. The examiner can normally be reached 8:30am-5:00pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Matthew Landau can be reached at 571-272-1731. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/TUCKER J WRIGHT/ Primary Examiner, Art Unit 2891
Prosecution Insights