DETAILED ACTION
This action is responsive to the following communications: the Application filed December 19, 2023, and Response to election / restriction filed December 11, 2025.
Claims 1-17 are pending. Claims 8-17 are withdrawn from consideration as being drawn to non-elected inventions without traverse. Claim 1 is independent.
Notice of Pre-AIA or AIA Status
The present application is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on December 19, 2023 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Specification
The title of the invention, SEMICONDUCTOR DEVICE, is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of AIA 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-5 and 7 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lee (US 2022/0077151).
Regarding independent claim 1, Lee discloses a semiconductor device (see e.g., FIG. 5A) comprising:
a bit line (BL) extending in a third direction (D1 direction);
a plurality of active layers (ACT) extending in a first direction (D2 direction) and contacting the bit line (BL);
a plurality of word lines (WL) extending in a second direction (D3 direction) and each disposed at a top surface or bottom surface of each of the plurality of active layers (ACT);
a plurality of capacitors (CAP) contacting the plurality of active layers (ACT); and
a contact formed (BLC and para. 0038: bit line contact node BLC) in at least one active layer disposed at an uppermost part of the bit line (i.e., BLC disposed not only uppermost part of the bit line, but also the rest part of the bit line), among the plurality of active layers (ACT),
wherein the bit line (BL) and the contact (BLC) are electrically connected or separated by using (i.e., BLC bit line contact node stands for contacting node), as a control line, a word line disposed over the top surface or under the bottom surface of the at least one active layer, among the plurality of word lines (see e.g., FIG. 5A-B, and accompanying disclosure).
Regarding claim 2, which depends from claim 1, Lee discloses each of the plurality of active layers (e.g., FIGS. 5A-B: ACT) comprises: a first source/drain region contacting the bit line, a second source/drain region contacting each of the plurality of capacitors, and a channel disposed between the first source/drain region and the second source/drain region (see e.g., FIGS. 5A-B and accompanying disclosure).
Regarding claim 3, which depends from claim 2, Lee discloses the contact (e.g., FIGS. 5A-B: BLC) is formed in the second source/drain region of the at least one active layer of the plurality of active layers, and the contact is contacting a local bit line (see e.g., FIGS. 5A-B and accompanying disclosure).
Regarding claim 4, which depends from claim 1, Lee discloses the third direction is a direction orthogonal to a plane defined by the first direction and the second direction (FIG. 5A: D1-D3).
Regarding claim 5, which depends from claim 3, Lee discloses each of the plurality of capacitors (e.g., FIGS. 5A-B: CAP) comprises a storage node, a dielectric layer, and a plate node, and the storage node has a cylinder shape and is horizontally contacting the active layer, the dielectric layer is formed to cover inner and outer walls of the cylinder of the storage node, and the plate node is extended to the inner and outer walls of the cylinder on the dielectric layer (see e.g., FIGS. 5A-B and accompanying disclosure).
Regarding claim 7, which depends from claim 2, Lee discloses each of the plurality of word lines (e.g., FIG. 5B, 8B: WL) covers the channel and partially overlaps with the first and second source/drain regions (see e.g., FIGS. 5B, 8B, and accompanying disclosure).
Claim Rejections - 35 USC § 103
The following is a quotation of AIA 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 6 is rejected under AIA 35 U.S.C. 103 as being unpatentable over Lee (US 2022/0077151) in view of e.g., Wang (US 2019/0273084).
Regarding claim 6, Lee teaches the limitations of claim 3.
Lee’s device do not explicitly disclose the local bit line is electrically connected to a global bit line, and the local bit line and the global bit line are formed in different wafers.
However, multi-chip and/or multi-wafer (die) implemented in a single chip and/or wafter is a well-known technology for a type of memory fabrication for its purpose.
For support, of the above asserted facts, see for example, Wang, paragraph [0030]: embodiments of the disclosure include a short local bit line and a long global bit line. With metal-on-back technology, the short local bit line uses interconnects on the backside of a semiconductor wafer, while the long global bit line uses interconnects on a frontside of the semiconductor wafer.
It would have been obvious to one of ordinary skill in the art before the effective filing date to apply the teaching of Wang to the teaching of Lee such that a memory, as taught by Lee, utilizes a semiconductor manufacturing, as taught by Wang, for the purpose of optimizing memory fabrication, thereby improving semiconductor manufacturing cost.
Conclusion
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/SUNG IL CHO/Primary Examiner, Art Unit 2825