DETAILED ACTION
The Amendment filed April 24, 2026 has been entered. Claims 1-20 are pending. Claims 8-17 are withdrawn from consideration as being drawn to non-elected inventions without traverse. Claims 2 and 7 have been cancelled. Claims 18-20 have been added. Claim 1 is independent.
Specification
The Amendment to the Title filed April 24, 2026 is acceptable.
Claim Rejections - 35 USC § 103
The following is a quotation of AIA 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 4-5 and 19-20 are rejected under AIA 35 U.S.C. 103 as being unpatentable over Ryu et al. (US 2022/0122974).
Regarding independent claim 1, Ryu et al. teach a semiconductor device (see e.g., FIG. 1) comprising:
a plurality of transistors (TR) connected to a plurality of word lines (WL) including a plurality of active layers (ACT);
a plurality of memory cells (MCA) including a plurality of capacitors (CAP) connected to a bit line through the plurality of active layers respectively extending in a first direction; and
the bit line (BL) extending in a second direction;
a control (PC) transistor connected to a control line (e.g., para. 0021: … PC … control the memory cell …) being an uppermost transistor among the plurality of transistors and including a control active layer (see e.g., FIG. 1 and accompanying disclosure).
Ryu et al. do not explicitly disclose a top-level control peripheral circuit comprising a transistor and an active layer.
However, a control circuitry comprising a transistor and an active layer is a well-known technology for a type of memory array for its purpose.
For support, of the above asserted facts, see for example, Lee et al. (US 2023/0162768), the uppermost column of an array (FIG. 2: 206, dummy cells (transistors) for performing memory functions in memory array; and para. 0021: … PC may include … transistor …) comprising an active layer (see FIG. 4); see Itoh et al. (US 2003/0128574), FIG. 1, QT1, along with FIGS. 3-7, and accompanying disclosure.
It would have been obvious to one of ordinary skill in the art before the effective filing date to apply the teaching of Lee / Itoh et al. to the teaching of Ryu et al. such that a memory, as taught by Ryu et al., utilizes a control circuitry, as taught by Lee / Itoh et al., for the purpose positioning controlling circuity higher level than main memory in a memory array, thereby considering multi-level memory array.
Regarding claim 4, Ryu et al. teach the limitations of claim 1.
Ryu et al. further teach the third direction is a direction orthogonal to a plane defined by the first direction and the second direction (FIG. 1).
Regarding claim 5, Ryu et al. teach the limitations of claim 1.
Ryu et al. further teach each of the plurality of capacitors (e.g., FIG. 1: CAP) comprises a storage node, a dielectric layer, and a plate node, and the storage node has a cylinder shape and is horizontally contacting the active layer, the dielectric layer is formed to cover inner and outer walls of the cylinder of the storage node, and the plate node is extended to the inner and outer walls of the cylinder on the dielectric layer (see e.g., FIG. 1 and accompanying disclosure).
Regarding claims 19-20, Ryu et al. teach the limitations of claim 1.
Ryu et al. further teach the plurality of word lines, the plurality of capacitors, the bit line and the control line are formed in a cell wafer, wherein a sense amplifier is formed in a peripheral wafer, and wherein the cell wafer and the peripheral wafer are different each other; the cell wafer and the peripheral wafer are bonded together using at least one bonding pad (e.g., para. 0055-0056: … through the wafer bonding …; further this is an inherent characteristic in memory packages).
Allowable Subject Matter
Claims 3, 6 and 18 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Response to Argument
Applicant’s arguments filed 04/24/2026, with respect to the rejection(s) of claims under 35 USC 102 and 103, have been fully considered but are moot in view of the new ground(s) of rejection
Therefore, it is respectfully submitted that the examiner maintains the rejection.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SUNG IL CHO whose telephone number is (571)270-0137. The examiner can normally be reached on M-Th, 7:30AM-5PM; Every other F, 7:30AM-4PM EST.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Alexander G Sofocleous can be reached on 571-272-0635. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/SUNG IL CHO/ Primary Examiner, Art Unit 2825
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