DETAILED ACTION
This Action is responsive to the Restriction/Election Response filed on 08/07/2026.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Election/Restrictions
Applicants’ election without traverse of Group I, drawn to a semiconductor device, in the reply filed on 08/07/2026 is acknowledged and entered into the record.
Claims 13-22 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected Group II, drawn to a method for forming a semiconductor device, there being no allowable generic or linking claim.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 5-6, and 8-10 are rejected under 35 U.S.C. 103 as being unpatentable over Chen (US 2022/0336650), in view of Lai (US 2024/0421194).
Regarding claim 1, Chen (see, e.g., FIG. 7) discloses a semiconductor device comprising:
a silicon (Si) base substrate 101 (Para 0020);
a first device region Rb formed over the Si base substrate 101, wherein the first device region Rb comprises (Para 0027):
a gallium nitride (GaN) layer 106 formed over the Si base substrate 101 (Para 0020);
a transition layer 104 disposed between the GaN layer 106 and the Si base substrate 101 (Para 0020);
a channel region 108 (left side of 142) formed in the GaN layer 106 (Para 0020);
first and second current-carrying electrodes 164b, 162b formed over the GaN layer 106, electrically coupled to a first active area 108 (left side of 142), 152b, 154b, and configured to support a current flow within the first active area 108 (left side of 142), 152b, 154b (Para 0037); and
a first control electrode 166b formed over the GaN layer 106, electrically coupled to the first active area 108 (left side of 142), 152b, 154b, and configured to control the current flow between the first and second current-carrying electrodes 164b, 162b (Para 0037);
a second device region Ra formed laterally adjacent the first device region Rb, wherein the second device region Ra comprises (Para 0027):
a first Si layer 130 (e.g., silicon nitride) formed over the Si base substrate 101 (Para 0026);
third and fourth current-carrying electrodes 162a, 164a formed over the first Si layer 130 (e.g., silicon nitride), and configured to support a current flow within an active area 108 (right side of 142), 152a, 154a of the second device region Ra (Para 0020, Para 0034, Para 0037); and
a second control electrode 166a formed over the first Si layer 130 (e.g., silicon nitride), electrically coupled to the second device region Ra, and configured to control the current flow between the third and fourth current-carrying electrodes 162a, 164a (Para 0037),
Although Chen shows substantial features of the claimed invention, Chen fails to expressly teach a silicon (Si) base substrate having a first crystal orientation; and a transition layer having a second crystal orientation.
Lai (see, e.g., FIG. 2), on the other hand, teaches a silicon (Si) base substrate 102 having a first crystal orientation e.g., 111; and a transition layer 104 having a second crystal orientation e.g., 111 for the purpose of minimizing lattice mismatch and promoting subsequent growth of GaN layers (Para 0020, Para 0043).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the silicon base substrate and the transition layer of Chen to a silicon (Si) base substrate having a first crystal orientation and a transition layer having a second crystal orientation as described by Lai for the purpose of minimizing lattice mismatch and promoting subsequent growth of GaN layers (Para 0020, Para 0043).
Regarding claim 5, Chen (see, e.g., FIG. 7) teaches the semiconductor device of claim 1, wherein the transition layer 104 may include a material selected from the group consisting of silicon, silicon carbide, gallium nitride, and aluminum nitride (Para 0020).
Regarding claim 6, Chen (see, e.g., FIG. 7) teaches the semiconductor device of claim 1, further comprising a passivation dielectric region 142 formed between a first sidewall e.g., right sidewall of 108 in Rb region of the first device region Rb and a second sidewall e.g., left sidewall of 108 in Ra region of the second device region Ra (Para 0027-Para 0029).
Regarding claim 8, Chen (see, e.g., FIG. 7) teaches the semiconductor device of claim 1, wherein a first upper surface e.g., upper surface of 132 in Rb region of the first device region Rb and a second upper surface e.g., upper surface of 132 in Ra region of the second device region Ra are co- planar.
Regarding claim 9, Chen (see, e.g., FIG. 7) teaches the semiconductor device of claim 1, wherein: the first current-carrying electrode 164b is configured as a first source electrode (Para 0036, Para 0038); the second current-carrying electrode 162b is configured as a first drain electrode (Para 0038); and the first control electrode 166b is configured as a first gate electrode (Para 0038).
Regarding claim 10, Chen (see, e.g., FIG. 7) teaches the semiconductor device of claim 9, wherein: the third current-carrying electrode 164a is configured as an element selected from the group consisting of a source electrode and an emitter electrode (Para 0038); the fourth current-carrying electrode 162a is configured as an element selected from the group consisting of a drain electrode and a collector electrode (Para 0038); and the second control electrode 166a is configured as an element selected from the group consisting of a gate electrode and a base electrode (Para 0038).
Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over Chen (US 2022/0336650), in view of Lai (US 2024/0421194), and further in view of Liu (US 2020/0243517).
Regarding claim 7, although Chen/Lai show substantial features of the claimed invention, Chen/Lai fail to expressly teach the semiconductor device of claim 6, wherein the passivation dielectric region includes silicon nitride.
Liu (see, e.g., FIG. 2), on the other hand, teaches passivation dielectric region e.g., isolation regions includes silicon nitride for the purpose of providing a material suitable for isolating active regions (Para 0083).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the material of the passivation dielectric region of Chen to include silicon nitride as described by Liu for the purpose of providing a material suitable for isolating active regions (Para 0083).
Allowable Subject Matter
Claims 2-4 and 11-12 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ANTONIO CRITE whose telephone number is (571) 270-5267. The examiner can normally be reached Monday - Friday, 10:00 am - 6:30 pm.
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/ANTONIO B CRITE/Primary Examiner, Art Unit 2817
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