DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s arguments, see pages 7-10, filed April 06, 2026, with respect to the rejection(s) of claims 11, 16-17 under U.S.C. 102 and 1-7, 10, 12-13 and 18 under U.S.C. 103 have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. A new ground(s) of rejection is necessitated by the amendment. Applicant’s arguments with respect to claims 1-7, 10-13 and 16-18 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 11, 16-17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Sudo et al. JPH05203698 (hereinafter referred to as Sudo) in view of Cheng et al. CN 116593853 A (hereinafter referred to as Cheng).
Regarding claim 11, Sudo discloses a system (fig. 2), comprising: a transistor (fig. 2, MESFET1, par[0004]-[0006]), wherein the transistor includes a control terminal (fig. 2, gate G, par. [0004]-[0006]), a first current carrying terminal (fig. 2, drain D, par. [0004]-[0006]), and a second current carry terminal (fig. 2, source S, par. [0004]-[0006]) and the transistor is forward biased (applying a forward voltage VGSF between the gate and the source, par. [0014]), the controller (computer, par. [0008]) being configured to: cause a voltage source (fig. 2, voltage source 18, par. [0004]-[0006]) to forward-bias the transistor, determine a thermal slope (par. [0014]), of the control terminal of the transistor, measure a first voltage V1 (fig. 2, voltmeter 14, par. [0004]-[0006]) of the control terminal of the transistor, measure a magnitude of a current ID (fig. 2, ammeter 17, par. [0004]-[0006]) flowing into the first current carrying terminal of the transistor (fig. 2, MESFET1, par. [0004]-[0006]), and determine a thermal resistance characteristic (par. [0006]) of the transistor using the first voltage, the second voltage, and the magnitude of the current.
Sudo does not explicitly disclose a system, comprising: a controller configured to couple to a transistor; apply a single voltage pulse across a first current carrying terminal of the transistor and a second current carrying terminal of the transistor, wherein a duration of the single voltage pulse is between 200 millisecond and 800 milliseconds, within one millisecond of an end of the single voltage pulse, measure a second voltage V2 of the control terminal of the transistor.
However Cheng discloses a system, comprising: a controller (fig. 1, central controller, pg. 5) configured to couple to a transistor (fig. 1, transistor device, pg. 5); after measuring the first voltage V1, (collecting the input pulse voltage signal VG through a channel of the oscilloscope), apply a single voltage pulse (fig. 1, long pulse width pulse voltage signal VG, pg. 5) across the first current carrying terminal and the second current carrying terminal of the transistor, wherein a duration of the single voltage pulse is (the gate pulse signal can flexibly select different pulse widths as required, pg. 5), within one millisecond of an end of the single voltage pulse measure a second voltage V2 (a pulse width of 100 ns is applied to the gate of the transistor device to be tested, and then the gate voltage VG of the transistor device to be tested is read through a high bandwidth oscilloscope with a sampling rate of 80GS/s, pg. 5), (gate voltage VG of the transistor device to be tested is read through a high bandwidth oscilloscope) of the control terminal of the transistor.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provide a simple measuring method for extracting thermal characteristic parameter of transistor device, through high time resolution fast test, as taught in Cheng in modifying the apparatus of Sudo. The motivation would be to accurately extract the thermal resistance, which can provide the reference basis for the circuit design and optimize the thermal impedance design of device. (see Cheng: abs.).
Regarding the duration of the voltage pulse: Suda and Cheng discloses a volage pulsewidth of 100 ns but does not disclose a particular value for this parameter however discloses that the gate pulse signal can flexibly select different pulse widths as required. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provide a single voltage pulse with a duration between 200 millisecond and 800 milliseconds, since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the “optimum range” involves only routine skill in the art. In re Aller, 105 USPQ 233. See MPEP 2144.05.
Regarding claim 16, Sudo discloses a method, comprising: forward-biasing a transistor (applying a forward voltage VGSF between the gate and the source, par. [0014]), the transistor (fig. 2, MESFET1, par[0004]-[0006]) including a control terminal (fig. 2, gate G, par. [0004]-[0006]), a first current carrying terminal (fig. 2, drain D, par. [0004]-[0006]), and a second current carry terminal (fig. 2, source S, par. [0004]-[0006]); measuring a first voltage VGS1 (fig. 2, voltmeter 14, par. [0004]-[0006]) of the control terminal of the transistor; measuring a magnitude of a current ID (fig. 2, ammeter 17, par. [0004]-[0006]) flowing into the first current carrying terminal of the transistor, and determining a thermal resistance characteristic (par. [0006]) of the transistor using the first voltage, the second voltage, and the magnitude of the current.
Sudo does not disclose a system, comprising: after measuring the first voltage VGS1, apply a single voltage pulse across a first current carrying terminal of the transistor and a second current carrying terminal of the transistor, wherein a duration of the single voltage pulse is between 200 millisecond and 800 milliseconds, within one millisecond of an end of the single voltage pulse, measure a second voltage VGS2 of the control terminal of the transistor.
However Cheng discloses a system, comprising: a controller (fig. 1, central controller, pg. 5) configured to couple to a transistor (fig. 1, transistor device, pg. 5); after measuring the first voltage V1, (collecting the input pulse voltage signal VG through a channel of the oscilloscope),apply a single voltage pulse (fig. 1, long pulse width pulse voltage signal VG, pg. 5) across the first current carrying terminal and the second current carrying terminal of the transistor, wherein a duration of the single voltage pulse is (the gate pulse signal can flexibly select different pulse widths as required, pg. 5), within one millisecond of an end of the single voltage pulse measure a second voltage VGS2 (a pulse width of 100 ns is applied to the gate of the transistor device to be tested, and then the gate voltage VG of the transistor device to be tested is read through a high bandwidth oscilloscope with a sampling rate of 80GS/s, pg. 5), (gate voltage VG of the transistor device to be tested is read through a high bandwidth oscilloscope) of the control terminal of the transistor.
The references are combined for the same reason already applied in the rejection of claim 11.
Regarding the duration of the voltage pulse: Suda and Cheng discloses a volage pulsewidth of 100 ns but does not disclose a particular value for this parameter however discloses that the gate pulse signal can flexibly select different pulse widths as required. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provide a single voltage pulse with a duration between 200 millisecond and 800 milliseconds, since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the “optimum range” involves only routine skill in the art. In re Aller, 105 USPQ 233. See MPEP 2144.05.
Regarding claim 17, Sudo discloses the method of claim 16, further comprising: determining a thermal slope (fig. 5, temperature coefficient k. k = ΔVGSF / ΔTch ,par. [0014]-[0015]) of the control terminal of the transistor (fig. 2, MESFET1, par[0004]-[0006]), wherein the thermal slope defines a relationship between a voltage (fig. 5, gate-source voltage VG, par. [0014]-[0015]) of the control terminal and a temperature of the transistor; and determining the thermal resistance (fig. 5, thermal resistance Rth, par. [0006], [0014]-[0015]) using the thermal slope of the control terminal.
Claim(s) 1-3 and 7 is/are rejected under 35 U.S.C. 103 as being unpatentable over Sudo in view of Chen et al. CN 116879702 A (hereinafter referred to as Chen).
Regarding claim 1, Sudo discloses a system (fig. 1-2, measuring circuit is a circuit for measuring the thermal resistance of MESFET1, par. [0003]), comprising: a first voltage source (fig. 2, voltage source 18, par. [0004]-[0006]) configured to connect to a control terminal (fig. 2, gate G, par. [0004]-[0006]) of a transistor (fig. 2, MESFET1, par. [0004]-[0006]); and to apply a forward-bias voltage to the control terminal of the transistor (applying a forward voltage VGSF between the gate and the source, par. [0004]-[0006], [0014]), measure a first voltage VGS1 (fig. 2, voltmeter 14, par. [0004]-[0006]) of the control terminal of the transistor (fig. 2, measuring the gate-source voltage VGS1, par. [0010]), after measuring the first voltage VGS1 (par. [0010]-[0011]), apply voltage pulse across a first current carrying terminal (fig. 2, source of the MESFET, par. [0011]) of the transistor and a second current carrying terminal (fig. 2, drain voltage, par. [0011]) of the transistor; measure a magnitude of a current ID (fig. 2, ammeter 17, par. [0004]-[0006]) flowing into the first current carrying terminal of the transistor, and determine a thermal resistance characteristic (par. [0006]) of the electronic device using the first voltage VGSI, the second voltage VGS2, and the magnitude of the current ID (par. [0004]-[0006]).
Sudo does not disclose a controller configured to: operate the first voltage source apply a single voltage pulse across a first current carrying terminal of the transistor and a second current carrying terminal of the transistor, wherein a duration of the single voltage pulse is between 200 millisecond and 800 milliseconds, within one millisecond of an end of the single voltage pulse, measure a second voltage VGS2 of the control terminal of the transistor; a transistor contained within an electronic device; compare the thermal resistance characteristic to a threshold value; and based on the comparison of the thermal resistance characteristic to the threshold value, determine that the electronic device has a defect that will prevent the electronic device from operating effectively.
However Cheng discloses a system, comprising: a controller (fig. 1, central controller, pg. 5) operate the first voltage source (pulse signal generator, pg. 5); configured to couple to a transistor (fig. 1, transistor device, pg. 5); apply a single voltage pulse (fig. 1, long pulse width pulse voltage signal VG, pg. 5) across the first current carrying terminal and the second current carrying terminal of the transistor (clm. 1), wherein a duration of the single voltage pulse is (the gate pulse signal can flexibly select different pulse widths as required, pg. 5), within one millisecond of an end of the single voltage pulse measure a second voltage V2 (a pulse width of 100 ns is applied to the gate of the transistor device to be tested, and then the gate voltage VG of the transistor device to be tested is read through a high bandwidth oscilloscope with a sampling rate of 80GS/s, pg. 5), (gate voltage VG of the transistor device to be tested is read through a high bandwidth oscilloscope) of the control terminal of the transistor.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provide a simple measuring method for extracting thermal characteristic parameter of transistor device, through high time resolution fast test, as taught in Cheng in modifying the apparatus of Sudo. The motivation would be to accurately extract the thermal resistance, which can provide the reference basis for the circuit design and optimize the thermal impedance design of device. (see Cheng: abs.).
Regarding the duration of the voltage pulse: Suda and Cheng discloses a volage pulsewidth of 100 ns but does not disclose a particular value for this parameter however discloses that the gate pulse signal can flexibly select different pulse widths as required. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provide a single voltage pulse with a duration between 200 millisecond and 800 milliseconds, since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the “optimum range” involves only routine skill in the art. In re Aller, 105 USPQ 233. See MPEP 2144.05.
Chen discloses a transistor (fig. 2, 10-SiC chip) contained within an electronic device (fig. 2, power cycle test circuit, content of the invention: 2nd par.); and a controller (fig. 7, processing module 60), compare the thermal resistance characteristic (fig. 4, step S400-S310) to a threshold value (fig. 4, step S420); and based on the comparison of the thermal resistance characteristic to the threshold value, determine that the electronic device has a defect that will prevent the electronic device from operating effectively (fig. 4, step S420-S440) (content of the invention: 7th par.), (clm. 4).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provide a diagnostic method of SiC MOSFET power cycle degradation mechanism to monitor and distinguish the degradation state of the chip and package, as taught in Chen in modifying the apparatus of Sudo and Cheng. The motivation would be the reason for the failure of the SiC MOSFET can be determined (see Chen: abs.).
Regarding claim 2, Sudo and Cheng and Chen discloses the system of claim 1, Sudo discloses wherein the controller is configured to: determine a thermal slope (fig. 5, temperature coefficient k. k = ΔVGSF / ΔTch ,par. [0014]-[0015]) of the control terminal of the transistor (fig. 2, MESFET1, par[0004]-[0006]), wherein the thermal slope defines a relationship between a voltage (fig. 5, gate-source voltage VG, par. [0014]-[0015]) of the control terminal and a temperature of the electronic device; and determine the thermal resistance (fig. 5, thermal resistance Rth, par. [0006], [0014]-[0015]) using the thermal slope of the control terminal.
Regarding claim 3, Sudo and Cheng and Chen discloses the system of claim 1, Sudo discloses wherein the controller is configured to determine the thermal resistance using the expression (VGS2-VGS1)/(thermal slope)/VGS2 * It (clm. 1)
Regarding claim 7, Sudo and Cheng and Chen discloses the system of claim 1, Sudo discloses further comprising a switch (fig. 2, switch 13, par. [0004]) connected to the first current carrying terminal (fig. 2, drain D, par. [0004]) and a second voltage source (fig. 2, voltage source 19, par. [0004]) connected to the switch, wherein when the switch is closed a voltage of the second voltage source is applied to the first current carrying terminal (fig. 2, 3, turns on the switch S13 at time T3, the drain-source for raising the channel temperature applying a voltage VDS by the voltage source 19 to the MESFET1, par. [0004]-[0014]).
Claim(s) 4-6 is/are rejected under 35 U.S.C. 103 as being unpatentable over Sudo in view of Chen as applied to claim 2 above, and further in view of Kanzawa (hereinafter referred to as Kanzawa).
Regarding claim 4, Sudo, Cheng and Chen discloses the system of claim 2, Sudo, Cheng and Chen discloses do not disclose the further comprising a heating element in thermal communication with the electronic device, wherein: the controller is coupled to the heating element; the controller is configured to determine a temperature of the electronic device; the controller is configured to determine the thermal slope by:
Sudo discloses measuring a third voltage VGS3 (fig. 2, voltmeter 14, par. [0004]-[0006]) of the control terminal of the transistor; determining a first temperature Ti of the electronic device; measuring a fourth voltage VGS4 (fig. 2, voltmeter 14 measure the voltage VGS (= VGS2), par. [0004]-[0006]) of the control terminal of the transistor; and determining the thermal slope using the expression
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(fig. 5, temperature coefficient k. k = ΔVGSF / ΔTch, par. [0014]-[0015]).
Kanzawa discloses the further comprising a heating element (fig. 2, plate 134, par. [0031]) in thermal communication with the electronic device (fig. 2, transistor 117, par. [0031]), wherein: the controller (fig. 2, control circuit 133, par. [0037]-[0038]) is coupled to the heating element; the controller is configured to determine a temperature of the electronic device (par. [0036]-[0038]); operating the heating element to modify a temperature of the electronic device (fig. 2. Elm. 117, par. [0035]); determining a second temperature T2 of the electronic device (par. [0036]-[0038]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provide temperature controlling device to maintain the transistor at a specified value or a predetermined temperature, as taught in Kanzawa in modifying the apparatus of Sudo and Cheng and Chen discloses. The motivation would be to maintain the transistor at a specified value or a predetermined temperature. (see Kanzawa: par. [0035]).
Regarding claim 5, Sudo, Cheng, Chen and Kanzawa discloses the system of claim 4, Kanzawa discloses wherein the electronic device (fig. 2, transistor 117, par. [0031]), and the heating element (fig. 2, plate 134, par. [0031]) are disposed within a thermally insulative housing (fig. 2, elm. 136, par. [0031]).
The references are combined for the same reason already applied in the rejection of claim 4.
Regarding claim 6, Sudo, Cheng, Chen and Kanzawa discloses the system of claim 4, Sudo discloses wherein the first current carrying terminal (fig. 2, drain D, par. [0004]) of the transistor (fig. 2, MESFET1, par. [0004]) is electrically connected to the second current carrying terminal (fig. 2, source S, par. [0004]) of the transistor when the controller (computer, par. [0008]) measures the third voltage VGS3 (fig. 2, voltmeter 14, par. [0004]-[0006])and the fourth voltage VGS4 (fig. 2, voltmeter 14 measure the voltage VGS (= VGS2), par. [0004]-[0006]).
Claim(s) 10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Sudo in view of Cheng in view of Chen in view of Kanzawa as applied to claim 4 above, and further in view of Yohei et al. A High Power Curve Tracer for Characterizing Full Operational Range of SiC Power Transistors, IEEE Xplore, ICMTS, May 2016, Pages 90-94. (hereinafter referred to as Yohei).
Regarding claim 10, Sudo, Cheng, Chen and Kanzawa discloses the system of claim 4, Sudo, Chen and Kanzawa do not disclose wherein a magnitude of a voltage of the single voltage pulse is equal to or greater than five volts.
Yohei discloses wherein a magnitude of a voltage of the single voltage pulse is equal to or greater than five volts (fig. 8-9, pg. 92, IV. Exper.).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provide voltages and currents in the short time pulse measurements, as taught in Yohei in modifying the apparatus of Sudo, Cheng, Chen, Kanzawa. The motivation would accurate characterization of such devices in entire operation region is for using wide bandgap semiconductors, such as SiC-MOSFET and SiC-JFET (see Yohei: Conclusion).
Claim(s) 12-14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Sudo in view of Cheng as applied to claim 11 above, and further in view of Kanzawa et al. JP 2023065319 A.
Regarding claim 12, Sudo and Cheng discloses the system of claim 11, Sudo does not disclose further comprising a heating element in thermal communication with the transistor, wherein: the controller is coupled to the heating element and is configured to; determine a temperature of the electronic device;
Sudo discloses determine the thermal slope (fig. 5, temperature coefficient k. k = ΔVGSF / ΔTch ,par. [0014]-[0015]) by: measuring a third voltage VGS3 of the control terminal (fig. 2, gate G, par. [0004]-[0006]) of the transistor; measuring a fourth voltage VGS4 (fig. 2, voltmeter 14 measure the voltage VGS (= VGS2), par. [0004]-[0006]) of the control terminal of the transistor; and determining the thermal slope using the expression (VGS3- VGS4)/(T1-T2) (fig. 5, temperature coefficient k. k = ΔVGSF / ΔTch ,par. [0014]-[0015])
Kanzawa discloses a heating element (fig. 2, plate 134, par. [0031]) in thermal communication with the transistor (fig. 2, transistor 117, par. [0031]), wherein: the controller (fig. 2, control circuit, par. [0037]-[0038]) is coupled to the heating element and is configured to; determine a temperature of the electronic device (par. [0037]-[0038]); determining a first temperature T1 of the transistor; operating the heating element to modify a temperature of the transistor (par. [0037]-[0038]); determining a second temperature T2 of the transistor (par. [0036]-[0038]);
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provide temperature controlling device to maintain the transistor at a specified value or a predetermined temperature, as taught in Kanzawa in modifying the apparatus of Sudo and Cheng. The motivation would be to maintain the transistor at a specified value or a predetermined temperature. (see Kanzawa: par. [0035]).
Regarding claim 13, Sudo, Cheng and Kanzawa discloses the system of claim 12, Sudo further comprising a switch (fig. 2, switch 13, par. [0004]) connected to the first currently carrying terminal (fig. 2, drain D, par. [0004]) and a second voltage source (fig. 2, voltage source 19, par. [0004]) connected to the switch, wherein when the switch is closed a voltage of the second voltage source is applied to the first current carrying terminal (fig. 2, 3, turns on the switch S13 at time T3, the drain-source for raising the channel temperature applying a voltage VDS by the voltage source 19 to the MESFET1, par. [0004]-[0014]).
Claim(s) 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Sudo in view of Cheng as applied to claim 17 above, and further in view of Kanzawa.
Regarding claim 18, Sudo discloses the method of claim 17, further comprising determining the thermal slope by: measuring a third voltage V3 (fig. 2, voltmeter 14, par. [0004]-[0006]) of the control terminal of the transistor (fig. 2, MESFET1, par[0004]-[0006]); measuring a fourth voltage V4 (fig. 2, voltmeter 14 measure the voltage VGS (= VGS2), par. [0004]-[0006]) of the control terminal of the transistor; and determining the thermal slope using the expression (fig. 5, temperature coefficient k. k = ΔVGSF / ΔTch ,par. [0014]-[0015])
Sudo does not disclose determining a first temperature Ti of the transistor operating the heating element to modify a temperature of the transistor; determining a second temperature T2 of the electronic device;
Kanzawa discloses disclose determining a first temperature Ti of the transistor (par. [0036]-[0038]); operating the heating element fig. 2, plate 134, par. [0031]) to modify a temperature of the transistor (fig. 2. Elm. 117, par. [0035]); determining a second temperature T2 (par. [0036]-[0038]) of the transistor;
The references are combined for the same reason already applied in the rejection of claim 12.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to COURTNEY G MCDONNOUGH whose telephone number is (571)272-6552. The examiner can normally be reached M-F 8 am-5 pm.
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/COURTNEY G MCDONNOUGH/Examiner, Art Unit 2858
/FARHANA A HOQUE/Primary Examiner, Art Unit 2858
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