Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 12/19/2023 was considered by the examiner.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 11, 16-17 is/are rejected under 35 U.S.C. 102(a)(1) as being clearly anticipated by Sudo et al. JPH05203698 (hereinafter referred to as Sudo).
Regarding claim 11, Sudo discloses a system, comprising: a controller configured to couple to a transistor (fig. 2, MESFET1, par[0004]-[0006]), wherein the transistor includes a control terminal (fig. 2, gate G, par. [0004]-[0006]), a first current carrying terminal (fig. 2, drain D, par. [0004]-[0006]), and a second current carry terminal (fig. 2, source S, par. [0004]-[0006]) and the transistor is forward biased (applying a forward voltage VGSF between the gate and the source, par. [0014]), the control being configured to: cause a voltage source (fig. 2, voltage source 18, par. [0004]-[0006]) to forward-bias the transistor, determine a thermal slope (par. [0014]), of the control terminal of the transistor measure a first voltage Vi (fig. 2, voltmeter 14, par. [0004]-[0006]) of the control terminal of the transistor, apply a voltage pulse (fig. 2, voltage source 19, par. [0004]-[0006]) across the first current carrying terminal and the second current carrying terminal of the transistor, measure a second voltage V2 (fig. 2, voltmeter 14 measure the voltage VGS (= VGS2), par. [0004]-[0006]) of the control terminal of the transistor; measure a magnitude of a current ID (fig. 2, ammeter 17, par. [0004]-[0006]) flowing into the first current carrying terminal of the transistor, and determine a thermal resistance characteristic (par. [0006]) of the electronic device using the first voltage, the second voltage, and the magnitude of the current.
Regarding claim 16, Sudo discloses a method, comprising: forward-biasing a transistor (applying a forward voltage VGSF between the gate and the source, par. [0014]), the transistor (fig. 2, MESFET1, par[0004]-[0006]) including a control terminal (fig. 2, gate G, par. [0004]-[0006]), a first current carrying terminal (fig. 2, drain D, par. [0004]-[0006]), and a second current carry terminal (fig. 2, source S, par. [0004]-[0006]); measuring a first voltage Vi (fig. 2, voltmeter 14, par. [0004]-[0006]) of the control terminal of the transistor, applying a voltage pulse (fig. 2, voltage source 19, par. [0004]-[0006]) across the first current carrying terminal and the second current carrying terminal of the transistor; measuring a second voltage V2 (fig. 2, voltmeter 14 measure the voltage VGS (= VGS2), par. [0004]-[0006]) of the control terminal of the transistor; measuring a magnitude of a current ID (fig. 2, ammeter 17, par. [0004]-[0006]) flowing into the first current carrying terminal of the transistor, and determining a thermal resistance characteristic (par. [0006]) of the electronic device using the first voltage, the second voltage, and the magnitude of the current.
Regarding claim 17, Sudo discloses the method of claim 16, further comprising: determining a thermal slope (fig. 5, temperature coefficient k. k = ΔVGSF / ΔTch ,par. [0014]-[0015]) of the control terminal of the transistor (fig. 2, MESFET1, par[0004]-[0006]), wherein the thermal slope defines a relationship between a voltage (fig. 5, gate-source voltage VG, par. [0014]-[0015]) of the control terminal and a temperature of the electronic device; and determining the thermal resistance (fig. 5, thermal resistance Rth, par. [0006], [0014]-[0015]) using the thermal slope of the control terminal.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Sudo.
Regarding claim 19, Applying the voltage pulse across the first current carrying terminal and the second current carrying terminal of the transistor for a time period having a duration that is less than 800 milliseconds. Sudo discloses across the first current carrying terminal and the second current carrying terminal of the transistor but does not disclose a particular value for this parameter. However, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention applying the voltage pulse across the first current carrying terminal and the second current carrying terminal of the transistor for a time period having a duration that is less than 800 milliseconds, since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the “optimum range” involves only routine skill in the art. In re Aller, 105 USPQ 233. See MPEP 2144.05.
Claim(s) 1-3 and 7-8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Sudo in view of Chen et al. CN 116879702 A (hereinafter referred to as Chen).
Regarding claim 1, Sudo discloses a system, comprising: a first voltage source (fig. 2, voltage source 18, par. [0004]-[0006]) configured to connect to a control terminal (fig. 2, gate G, par. [0004]-[0006]) of a transistor (fig. 2, MESFET1, par[0004]-[0006]); to apply a forward-bias voltage to the control terminal of the transistor ([0004]-[0006]]), (applying a forward voltage VGSF between the gate and the source, par. [0014]), and a controller (computer, par. [0008]) measure a first voltage VGS1 (fig. 2, voltmeter 14, par. [0004]-[0006]) of the control terminal of the transistor, apply a voltage pulse (fig. 2, voltage source 19, par. [0004]-[0006]) across a first current carrying terminal (fig. 2, drain D, par. [0004]-[0006]) of the transistor and a second current carrying terminal of the transistor (fig. 2, source S, par. [0004]-[0006]), measure a second voltage VGS2 (fig. 2, voltmeter 14 measure the voltage VGS (= VGS2), par. [0004]-[0006]) of the control terminal of the transistor; measure a magnitude of a current ID (fig. 2, ammeter 17, par. [0004]-[0006]) flowing into the first current carrying terminal of the transistor, and determine a thermal resistance characteristic (par. [0006]) of the electronic device using the first voltage VGSI, the second voltage VGS2, and the magnitude of the current ID (par. [0004]-[0006]); and
Sudo does not disclose a transistor contained within an electronic device; compare the thermal resistance characteristic to a threshold value; and based on the comparison of the thermal resistance characteristic to the threshold value, determine that the electronic device has a defect that will prevent the electronic device from operating effectively.
Chen discloses a transistor (fig. 2, 10-SiC chip) contained within an electronic device (fig. 2, power cycle test circuit, content of the invention: 2nd par.); and a controller (fig. 7, processing module 60), compare the thermal resistance characteristic (fig. 4, step S400-S310) to a threshold value (fig. 4, step S420); and based on the comparison of the thermal resistance characteristic to the threshold value, determine that the electronic device has a defect that will prevent the electronic device from operating effectively (fig. 4, step S420-S440) (content of the invention: 7th par.), (clm. 4).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provide a diagnostic method of SiC MOSFET power cycle degradation mechanism to monitor and distinguish the degradation state of the chip and package, as taught in Chen in modifying the apparatus of Sudo. The motivation would be the reason for the failure of the SiC MOSFET can be determined (see Chen: abs.).
Regarding claim 2, Sudo and Chen discloses the system of claim 1, Sudo discloses wherein the controller is configured to: determine a thermal slope (fig. 5, temperature coefficient k. k = ΔVGSF / ΔTch ,par. [0014]-[0015]) of the control terminal of the transistor (fig. 2, MESFET1, par[0004]-[0006]), wherein the thermal slope defines a relationship between a voltage (fig. 5, gate-source voltage VG, par. [0014]-[0015]) of the control terminal and a temperature of the electronic device; and determine the thermal resistance (fig. 5, thermal resistance Rth, par. [0006], [0014]-[0015]) using the thermal slope of the control terminal.
Regarding claim 3, Sudo and Chen discloses the system of claim 1, Sudo discloses wherein the controller is configured to determine the thermal resistance using the expression (VGS2-VGS1)/(thermal slope)/VGS2 * It (clm. 1)
Regarding claim 7, Sudo and Chen discloses the system of claim 1, Sudo discloses further comprising a switch (fig. 2, switch 13, par. [0004]) connected to the first currently carrying terminal (fig. 2, drain D, par. [0004]) and a second voltage source (fig. 2, voltage source 19, par. [0004]) connected to the switch, wherein when the switch is closed a voltage of the second voltage source is applied to the first current carrying terminal (fig. 2, 3, turns on the switch S13 at time T3, the drain-source for raising the channel temperature applying a voltage VDS by the voltage source 19 to the MESFET1, par. [0004]-[0014]).
Regarding claim 8, The controller is configured to close the switch for a time period having a duration that is between 200 millisecond and 800 milliseconds. Sudo and Chen discloses applying the voltage pulse and controller configured to close the switch but does not disclose a particular value for this parameter. However, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provide a controller configured to close the switch for a time period having a duration that is between 200 millisecond and 800 milliseconds, since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the “optimum range” involves only routine skill in the art. In re Aller, 105 USPQ 233. See MPEP 2144.05.
Claim(s) 4-6 is/are rejected under 35 U.S.C. 103 as being unpatentable over Sudo in view of Chen as applied to claim 2 above, and further in view of Kanzawa (hereinafter referred to as Kanzawa).
Regarding claim 4, Sudo and Chen discloses the system of claim 2, Sudo and Chen do not disclose the further comprising a heating element in thermal communication with the electronic device, wherein: the controller is coupled to the heating element; the controller is configured to determine a temperature of the electronic device; the controller is configured to determine the thermal slope by:
Sudo discloses measuring a third voltage VGS3 (fig. 2, voltmeter 14, par. [0004]-[0006]) of the control terminal of the transistor; determining a first temperature Ti of the electronic device; measuring a fourth voltage VGS4 (fig. 2, voltmeter 14 measure the voltage VGS (= VGS2), par. [0004]-[0006]) of the control terminal of the transistor; and determining the thermal slope using the expression
PNG
media_image1.png
23
46
media_image1.png
Greyscale
(fig. 5, temperature coefficient k. k = ΔVGSF / ΔTch, par. [0014]-[0015]).
Kanzawa discloses the further comprising a heating element (fig. 2, plate 134, par. [0031]) in thermal communication with the electronic device (fig. 2, transistor 117, par. [0031]), wherein: the controller (fig. 2, control circuit 133, par. [0037]-[0038]) is coupled to the heating element; the controller is configured to determine a temperature of the electronic device (par. [0036]-[0038]); operating the heating element to modify a temperature of the electronic device (fig. 2. Elm. 117, par. [0035]); determining a second temperature T2 of the electronic device (par. [0036]-[0038]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provide temperature controlling device to maintain the transistor at a specified value or a predetermined temperature, as taught in Kanzawa in modifying the apparatus of Sudo and Chen. The motivation would be to maintain the transistor at a specified value or a predetermined temperature. (see Kanzawa: par. [0035]).
Regarding claim 5, Sudo, Chen and Kanzawa discloses the system of claim 4, Kanzawa discloses wherein the electronic device (fig. 2, transistor 117, par. [0031]), and the heating element (fig. 2, plate 134, par. [0031]) are disposed within a thermally insulative housing (fig. 2, elm. 136, par. [0031]).
The references are combined for the same reason already applied in the rejection of claim 4.
Regarding claim 6, Sudo, Chen and Kanzawa discloses the system of claim 4, Sudo discloses wherein the first current carrying terminal (fig. 2, drain D, par. [0004]) of the transistor (fig. 2, MESFET1, par. [0004]) is electrically connected to the second current carrying terminal (fig. 2, source S, par. [0004]) of the transistor when the controller (computer, par. [0008]) measures the third voltage VGS3 (fig. 2, voltmeter 14, par. [0004]-[0006])and the fourth voltage VGS4 (fig. 2, voltmeter 14 measure the voltage VGS (= VGS2), par. [0004]-[0006]).
Claim(s) 9-10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Sudo in view of Chen as applied to claim 8/4 above, and further in view of Yohei et al. A High Power Curve Tracer for Characterizing Full Operational Range of SiC Power Transistors, IEEE Xplore, ICMTS, May 2016, Pages 90-94. (hereinafter referred to as Yohei).
Regarding claim 9, Sudo and Chen discloses the system of claim 8, Sudo and Chen do not disclose wherein the controller is configured to measure the second voltage within one millisecond of opening the switch.
Yohei discloses wherein the controller is configured to measure the second voltage within one millisecond of opening the switch (fig. 3,14, pg. 93, V. DIS.).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provide voltages and currents in the short time pulse measurements, as taught in Yohei in modifying the apparatus of Sudo and Chen. The motivation would accurate characterization of such devices in entire operation region is for using wide bandgap semiconductors, such as SiC-MOSFET and SiC-JFET (see Yohei: Conclusion).
Regarding claim 10, Sudo, Chen and Kanzawa discloses the system of claim 4, Sudo, Chen and Kanzawa do not disclose wherein a magnitude of a voltage of the voltage pulse is equal to or greater than five volts.
Yohei discloses wherein a magnitude of a voltage of the voltage pulse is equal to or greater than five volts (fig. 8-9, pg. 92, IV. Exper.).
The references are combined for the same reason already applied in the rejection of claim 9.
Claim(s) 12-14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Sudo as applied to claim 11 above, and further in view of Kanzawa et al. JP 2023065319 A.
Regarding claim 12, Sudo discloses the system of claim 11, Sudo does not disclose further comprising a heating element in thermal communication with the electronic device, wherein: the controller is coupled to the heating element and is configured to; determine a temperature of the electronic device;
Sudo discloses determine the thermal slope (fig. 5, temperature coefficient k. k = ΔVGSF / ΔTch ,par. [0014]-[0015]) by: measuring a third voltage VGS3 of the control terminal (fig. 2, gate G, par. [0004]-[0006]) of the transistor; measuring a fourth voltage VGS4 (fig. 2, voltmeter 14 measure the voltage VGS (= VGS2), par. [0004]-[0006]) of the control terminal of the transistor; and determining the thermal slope using the expression (VGS3- VGS4)/(T1-T2) (fig. 5, temperature coefficient k. k = ΔVGSF / ΔTch ,par. [0014]-[0015])
Kanzawa discloses a heating element (fig. 2, plate 134, par. [0031]) in thermal communication with the electronic device (fig. 2, transistor 117, par. [0031]), wherein: the controller (fig. 2, control circuit, par. [0037]-[0038]) is coupled to the heating element and is configured to; determine a temperature of the electronic device (par. [0037]-[0038]); determining a first temperature T1 of the electronic device; operating the heating element to modify a temperature of the electronic device (par. [0037]-[0038]); determining a second temperature T2 of the electronic device (par. [0036]-[0038]);
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provide temperature controlling device to maintain the transistor at a specified value or a predetermined temperature, as taught in Kanzawa in modifying the apparatus of Sudo. The motivation would be to maintain the transistor at a specified value or a predetermined temperature. (see Kanzawa: par. [0035]).
Regarding claim 13, Sudo and Kanzawa discloses the system of claim 12, Sudo further comprising a switch (fig. 2, switch 13, par. [0004]) connected to the first currently carrying terminal (fig. 2, drain D, par. [0004]) and a second voltage source (fig. 2, voltage source 19, par. [0004]) connected to the switch, wherein when the switch is closed a voltage of the second voltage source is applied to the first current carrying terminal (fig. 2, 3, turns on the switch S13 at time T3, the drain-source for raising the channel temperature applying a voltage VDS by the voltage source 19 to the MESFET1, par. [0004]-[0014]).
Regarding claim 14, When applying the voltage pulse, the controller is configured to close the switch for a time period having a duration that is between 200 millisecond and 800 milliseconds. Sudo and Kanzawa discloses applying the voltage pulse and controller configured to close the switch but does not disclose a particular value for this parameter. However, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention when applying the voltage pulse, the controller is configured to close the switch for a time period having a duration that is between 200 millisecond and 800 milliseconds, since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the “optimum range” involves only routine skill in the art. In re Aller, 105 USPQ 233. See MPEP 2144.05.
Claim(s) 15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Sudo in view of Kanzawa as applied to claim 14/16 above, and further in view of Yohei.
Regarding claim 15, Sudo and Kanzawa discloses the system of claim 14, Sudo and Kanzawa do not disclose wherein the controller is configured to measure the second voltage within one millisecond of opening the switch.
Yohei discloses wherein the controller is configured to measure the second voltage within one millisecond of opening the switch (fig. 3,14, pg. 93, V. DIS.).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provide voltages and currents in the short time pulse measurements, as taught in Yohei in modifying the apparatus of Sudo. The motivation would accurate characterization of such devices in entire operation region is for using wide bandgap semiconductors, such as SiC-MOSFET and SiC-JFET (see Yohei: Conclusion).
Regarding claim 20, Sudo discloses the method of claim 16, Sudo does not disclose further comprising measuring the second voltage within one millisecond of applying the voltage pulse across the first current carrying terminal and the second current carrying terminal of the transistor
Yohei discloses measuring the second voltage within one millisecond of applying the voltage pulse across the first current carrying terminal and the second current carrying terminal of the transistor (fig. 3,14, pg. 93, V. DIS.).
The references are combined for the same reason already applied in the rejection of claim 15.
Claim(s) 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Sudo as applied to claim 17 above, and further in view of Kanzawa.
Regarding claim 18, Sudo discloses the method of claim 17, further comprising determining the thermal slope by: measuring a third voltage V3 (fig. 2, voltmeter 14, par. [0004]-[0006]) of the control terminal of the transistor (fig. 2, MESFET1, par[0004]-[0006]); measuring a fourth voltage V4 (fig. 2, voltmeter 14 measure the voltage VGS (= VGS2), par. [0004]-[0006]) of the control terminal of the transistor; and determining the thermal slope using the expression (fig. 5, temperature coefficient k. k = ΔVGSF / ΔTch ,par. [0014]-[0015])
Sudo does not disclose determining a first temperature Ti of the electronic device; operating the heating element to modify a temperature of the electronic device; determining a second temperature T2 of the electronic device;
Kanzawa discloses disclose determining a first temperature Ti of the electronic device (par. [0036]-[0038]); operating the heating element fig. 2, plate 134, par. [0031]) to modify a temperature of the electronic device (fig. 2. Elm. 117, par. [0035]); determining a second temperature T2 (par. [0036]-[0038]) of the electronic device;
The references are combined for the same reason already applied in the rejection of claim 12.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to COURTNEY G MCDONNOUGH whose telephone number is (571)272-6552. The examiner can normally be reached M-F 8 am-5 pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, EMAN ALKAFAWI can be reached at (571) 272-4448. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/COURTNEY G MCDONNOUGH/Examiner, Art Unit 2858
/EMAN A ALKAFAWI/Supervisory Patent Examiner, Art Unit 2858 12/31/2025