DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1, 2, 7, 9, and 10 is/are rejected under 35 U.S.C. 102(a)(1) as being unpatentable over Nakanishi et al. US 2017/0301665 A1 (“Nakanishi”).
As to claim 1, Nakanishi discloses an I/O circuit formed by freely combining a plurality of kinds of standard cells included in a cell library,
wherein the plurality of kinds of standard cells include at least a first standard cell and a second standard cell (Paragraphs 7 or 50),
the first standard cell includes a first protection element (Figure 3 or Paragraphs 7 or 52 – e.g., the combination of a standard cell Elements 11 and 23-24 and protection circuit Element 21) and
a first power line formed in a region over the first protection element so as to conduct to the first protection element (Figure 3 or Paragraphs 7 or 52 – e.g., line 31), and
the second standard cell (Figure 3 or Paragraphs 7 or 52 – e.g., the combination of a standard cell Elements 12 and 25 and protection circuit Element 22) includes a second protection element formed in a layout identical with a layout of the first protection element (Figure 3 or Paragraph 57 – e.g., protection cells 21 and 22 have the same configuration) and
a second power line formed in a region over the second protection element so as to conduct to the second protection element while being isolated from the first power line (Figure 3 or Paragraphs 7 or 52 – e.g., line 32, Paragraph 60 – “can protect the second circuit from a surge occurring at the first circuit”).
As to claim 2, Nakanishi discloses the circuit of claim 1. Nakanishi further discloses wherein the plurality of kinds of standard cells are arrayed along a first direction, and the first power line is laid along the first direction (Figures 2-3 or Paragraphs 50-52 – e.g., “standard cells…disposed along the extending direction of power line”).
As to claim 7, Nakanishi discloses the circuit of claim 1. Nakanishi further discloses a first internal circuit connected to the first standard cell, the first internal circuit being configured to receive electric power from the first power line; and a second internal circuit connected to the second standard cell, the second internal circuit being configured to receive electric power from the second power line (Figure 3 – e.g., cells connected to VDD and VSS lines).
Claim 9 recites elements similar to claim 1, and is rejected for the same reasons.
As to claim 10, Nakanishi discloses the circuit of claim 9. Nakanishi further discloses a step of selecting, arranging, and freely combining the plurality of kinds of standard cells included in the cell library; and a step of laying power lines and signal lines so as to connect the plurality of kinds of freely combined standard cells to other circuit blocks (Figure 25 or Paragraphs 199-202 – e.g., cell arrangement and wiring steps).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Nakanishi.
As to claim 8, Nakanishi discloses the circuit of claim 7. Nakanishi does not explicitly disclose a pad configured to have the first and second standard cells both connected thereto. However, Nakanishi does teach the use of pins or pads for both external and internal connections, including the use of a shared pad with the protection circuit (Nakanishi Paragraphs 3, 42 or 168-170). It would have been obvious to one having ordinary skill in the art at the time the invention was made to have a pad configured to have the first and second standard cells both connected thereto because doing would allow the circuit to be configured in a way which would be protected from electrical surges.
Allowable Subject Matter
Claims 3-6 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
The prior art does not teach or suggest a I/O circuit having the combination of elements of the claims including, among other elements, the circuit element arrangement of claim 3 in combination with the cell, protection element, and powerline configuration of the independent claims.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to BRYCE M AISAKA whose telephone number is (571)270-5808. The examiner can normally be reached M-F: 6:30AM-5:00PM PT.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jack Chiang can be reached at (571)272-7483. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/BRYCE M AISAKA/Primary Examiner, Art Unit 2851
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