DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Claims 1-13, Group I, device in the reply filed on 4/8/2026 is acknowledged.
Claims 14-20 (Please note that claim 20 is newly added on 4/8/2026 that reads on Group II, method) are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected Group II, method, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 4/8/2026
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim 1, 4 and 11-13 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Hsu et al. (20210375883)
Regarding Claim 1, in Figs. 2, 4A and 7, Hsu et al. discloses a stacked static random access memory, SRAM, cell comprising: two first transistor structures (PU1, PU2); two second transistor structures (PD1, PD2); wherein the first transistor structures and the second transistor structures form a pair of cross-coupled inverters (see Fig. 2); one or two pass gate, PG, transistor structures; one or more first power rails VDD and/or one or more second power rails VDD arranged above the first and the second transistor structures, wherein the one or more first power rails are connected by respective first vias to at least one of the first transistor structures from above, and/or the one or more second power rails are connected by respective second vias (232_1/232_2/232_3) (paragraph 0028, Fig. 4B) to at least one of the second transistor structures from above (Fig. 4B, 7), ; and one or two bit lines BL/BLB arranged below the PG transistor structures (Fig. 3, backside), wherein each bit line is connected by a respective third (backside via 312, Fig. 5, paragraph 0029 and particularly lines 8-17) via to one PG transistor structure from below (see Fig. 3, paragraph 0018, Fig. 5, paragraphs 0029 and 0032)
Regarding Claim 4, in Figs. 10 and paragraph 0045 of Hsu et al, a word line arranged WL1-WL8 below the PG transistor structures, wherein the word line is connected by one or two respective fourth vias to the one or two PG transistor structures from below.
Regarding Claim 11, in paragraphs 0015 and 0031 of Hsu et al., the transistor structures are nanosheet transistor structures, or fin transistor structures.
Regarding Claim 12, in Fig. 2 and paragraphs 0014, 0016, 0023 and 0024 of Hsu et al, the first transistor structures and the one or two PG transistor structures are PMOS transistor structures, and the second transistor structures are NMOS transistor structures; and/or the first transistor structures are pull-up, PU, transistor structures, and the second transistor structures are pull-down, PD, transistor structures of the SRAM cell; and wherein the one or more first power rails are configured to provide a supply voltage (VDD), and the one or more second power rails are configured to provide a ground voltage (VSS).
Regarding Claim 13, in Fig. 2 and paragraphs 0014, 0016, 0023 and 0024 of Hsu et al, the first transistor structures and the one or two PG transistor structures are NMOS transistor structures, and the second transistor structures are PMOS transistor structures; and/or the first transistor structures are PD transistor structures, and the second transistor structures are PU transistor structures; and wherein the one or more first power rails are configured to provide a ground voltage (VSS), and the one or more second power rails are configured to provide a supply voltage (VDD).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 2, 3 and 5-10 are rejected under 35 U.S.C. 103 as being unpatentable over Hsu et al. (20210375883) in view of Chanemougame et al. (20210202500)
Regarding Claim 2, Hsu eta l. discloses everything except to discloses plurality of stacked tiers, wherein at least one of the first, the second, or the PG transistor structures is formed in each of the tiers. However, Chanemougame et al. discloses a stacked CFET SRAM device where in Figs. 5A and 5B and in paragraph 0054, the required limitation where plurality of stacked tiers (decks), wherein at least one of the first, the second, or the PG transistor structures is formed in each of the tiers (decks)
It would have been obvious to one of having ordinary skill in the art before the effective filing date of the claimed invention to have the required stacked tiers in Hsu et al. as taught by Chanemougame et al. in order to vertically integrate and hence in order to have a compact SRAM device.
Regarding Claim 3, in Figs. 4A, 4B, 5A, 5B and paragraphs 0051,0052 and 0054 the first transistor structures are formed in a first tier of the SRAM cell; the second transistor structures are formed in a second tier of the SRAM cell, the second tier being arranged above the first tier; the one or two PG structures are formed in the first tier or in a third tier of the SRAM cell, the third tier being arranged below the first tier; and the first and the second power rails are arranged above the second tier, wherein the first power rails are connected by respective first vias to the first transistor structures from above, and the second power rails are connected by respective second vias to the second transistor structures from above.
Regarding Claim 5, Hsu et al. discloses everything except to discloses plurality of stacked tiers, wherein at least one of the first, the second, or the PG transistor structures is formed in each of the tiers. However, in Figs. 5A and 5B and paragraphs 0053 and 0054 of Chanemougame et al, the first transistor structures are formed in a first tier of the SRAM cell; the second transistor structures are formed in a second tier of the SRAM cell, the second tier being arranged above the first tier; the one or two PG structures are formed in the first tier or in a third tier of the SRAM cell, the third tier being arranged below the first tier; and the first and the second power rails are arranged above the second tier, wherein the first power rails are connected by respective first vias to the first transistor structures from above, and the second power rails are connected by respective second vias to the second transistor structures from above.
It would have been obvious to one of having ordinary skill in the art before the effective filing date of the claimed invention to have the required stacked tiers in Hsu et al. as taught by Chanemougame et al. in order to vertically integrate and hence in order to have a compact SRAM device.
Regarding Claim 6, Hsu et al. discloses everything except to discloses plurality of stacked tiers, wherein at least one of the first, the second, or the PG transistor structures is formed in each of the tiers. However, in Figs 15A and 15B and paragraphs 0082 and 0084 of Chanemougame et al, a plurality of stacked tiers, wherein at least one of the first, the second, or the PG transistor structures is formed in each of the tiers.
It would have been obvious to one of having ordinary skill in the art before the effective filing date of the claimed invention to have the required stacked tiers in Hsu et al. as taught by Chanemougame et al. in order to vertically integrate and hence in order to have a compact SRAM device.
Regarding Claim 7, in paragraph 0048, 0053 and 0054 and Figs. 5A and 5B of Chanemougame et al, the first transistor structures are formed in a first tier of the SRAM cell; the second transistor structures are formed in a second tier of the SRAM cell, the second tier being arranged above the first tier; the one or two PG structures are formed in the first tier or in a third tier of the SRAM cell, the third tier being arranged below the first tier; and the first and the second power rails are arranged above the second tier, wherein the first power rails are connected by respective first vias to the first transistor structures from above, and the second power rails are connected by respective second vias to the second transistor structures from above.
Regarding Claim 8, in Figs. 4B, 4C and 4D, elements 426 and 442 and paragraphs 0051 and 0052 of Chanemougame et al, a length of each third via is smaller than a height of the second tier; and/or a length of each fourth via is smaller than a height of the second tier.
Regarding Claim 9, Hsu et al. discloses everything except to disclose the tier structure. However, Chanemougame et al. discloses a stacked CFET SRAM device where in Figs. 5A and 5B and in paragraph 0054, a first PG transistor structure is formed in a first tier of the SRAM cell; the two first transistor structures and the two second transistor structures are formed, respectively, in a second tier, a third tier, a fourth tier, and a fifth tier of the SRAM cell, the second tier being arranged above the first tier, the third tier being arranged above the second tier, the fourth tier being arranged above the third tier, and the fifth tier being arranged above the fourth tier; a second PG transistor structure is formed in a sixth tier of the SRAM cell , the sixth tier being arranged above the fifth tier; a first bit line is arranged below the first tier and is connected by one third via to the first PG transistor structure from below; and a second bit line is arranged above the sixth tier and is connected by a fifth via to the second PG transistor structure from above.
It would have been obvious to one of having ordinary skill in the art before the effective filing date of the claimed invention to have the required stacked tiers in Hsu et al. as taught by Chanemougame et al. in order to vertically integrate and hence in order to have a compact SRAM device.
Regarding Claim 10, in paragraphs 0015 and 0031 of Hsu et al., the transistor structures are nanosheet transistor structures, or fin transistor structures, the transistor structures are nanosheet transistor structures, or fin transistor structures.
Cited Pertinent Prior Arts NOT Relied Upon
Examiner is including following pertinent prior arts that are NOT relied upon on this rejection but that do disclose stacked SRAM structure with 3-layere/leveled/tiered/decked configuration
Huyghebaert 20230189497, Figs. 8A-8B and paragraph 0089
Huang 20230137806
Xie 20240008242, Figs. 7A-7E, 8A-8E
Sharma 20230056640 Fig. 6
Moroz et al. 20150370947
Conclusion
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/FAZLI ERDEM/Primary Examiner, Art Unit 2812 4/17/2026
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