DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Komai et al. (US 2016/0284753 A1 hereinafter referred to as “Komai”).
With respect to claim 1, Komai discloses, in Figs.1-119, a solid-state imaging device, comprising: a substrate (12) including an imaging element (51) configured to generate an electric signal by photoelectric conversion of incident light/(light received) that is incident on a first surface/(surface from wich light is received) of the substrate (101) (see Par.[0342]-[0344] wherein the pixel sensor substrate 12, a multi-layer wiring layer 102 is formed on the lower side (the side of the logic substrate 11) of a semiconductor substrate 101 (hereinafter referred to as a silicon substrate 101) formed of a silicon (Si); see Par.[0318]-[0320] wherein the photodiode 51 is a photoelectric conversion portion that generates and accumulates a charge (signal charge) according to an amount of received light; it is submitted that received light cab only be through lens 16); and a conductor (106, 109, 103) in surface contact with at least one of a second surface/(bottom surface) of the substrate (101) that is opposite to the first surface/(upper surface) of the substrate (101), or a side surface of the substrate (101) that is continuous with the second surface of the substrate (101), wherein the side surface of the substrate (101) is electrically connected to the imaging element (51) (see Par.[0344]-[0346] wherein the multi-layer wiring layer 102 includes a plurality of wiring layers 103 including an uppermost-layer wiring layer 103a closest to the silicon substrate 101; see Par.[0377] wherein the basic structure illustrated in FIG. 5. That is, the logic substrate 11 and the pixel sensor substrate 12 are connected to the upper side of the pixel sensor substrate 12 by using the connection wiring 106 and the two through electrodes, i.e., the silicon through electrode 109 and the chip through electrode 105; see Par.[0419]-[0420] wherein the silicon through electrode 109 and the chip through electrode 105).
With respect to claim 3, Komai discloses, in Figs.1-119, the solid-state imaging device, wherein on the at least one of the second surface of the substrate (101) or the side surface of the substrate (101), an arrangement place of the conductor (103, 106, 109) is flush with the at least one of the second surface/(bottom surface) of the substrate (101) or the side surface of the substrate (101) (see Fig.5).
With respect to claim 4, Komai discloses, in Figs.1-119, the solid-state imaging device, further comprising a contact member (105, 83, 87) extending in a depth direction of the substrate, wherein the contact member is electrically connected to the imaging element, and the conductor is electrically connected to the contact member (see Par.[0360] wherein the silicon through electrode 109 and the chip through electrode 105; see Par.[0362] wherein the silicon through electrode 151 connected to the wiring layer 83c of the logic substrate 11 and the chip through electrode 152 connected to the wiring layer 103c of the pixel sensor substrate 12 are formed at predetermined positions of the silicon substrate 81 on the side of the logic substrate 11; see Par.[0513]-[0514] wherein as illustrated in FIG. 61, a barrier metal film (not illustrated) and a Cu seed layer 231 are formed by a sputtering method. The barrier metal film is a film preventing the connection conductor 87 (Cu) from diffusing and the Cu seed layer 231 becomes an electrode when the connection conductor 87 is embedded by an electrolytic plating method. As the material of the barrier metal film, for example, tantalum (Ta), titanium (Ti), tungsten (W), zirconium (Zr), a nitride film thereof, or a carbonized film thereof can be used).
With respect to claim 5, Komai discloses, in Figs.1-119, the solid-state imaging device, wherein the substrate (11) further includes a signal output unit configured to: transmit a first signal to the imaging element; and receive a second signal to and from the imaging element, and the signal output unit is connected to an end of the contact member (see Par.[0868], [0922] wherein a semiconductor device includes a first semiconductor substrate in which a pixel region where pixel portions performing photoelectric conversion are two-dimensionally arranged is formed and a second semiconductor substrate in which a logic circuit processing a pixel signal output from the pixel portion is formed).
With respect to claim 6, Komai discloses, in Figs.1-119, the solid-state imaging device, wherein the substrate further includes: a first substrate (12), wherein the imaging element (51) includes a photoelectric conversion unit, the photoelectric conversion unit is on the first substrate (12), and the photoelectric conversion unit is configured to perform the photoelectric conversion; and a second substrate (11) on the first substrate (12), wherein the second substrate is configured to perform a signal processing operation (35) on the electric signal that is photoelectrically converted by the photoelectric conversion unit, and the contact member extends in each of a depth direction of the first substrate and a depth direction of the second substrate (see Par.[0307] wherein the pixel 32 includes a photodiode serving as a photoelectric conversion element and a plurality of pixel transistors; see Par.[0310]-[0311] wherein the pixel array unit 33 sequentially in units of rows in the vertical direction and supplies a pixel signal based on a signal charge generated according to an amount of light received in the photoelectric conversion portion of each pixel 32 to the column signal processing circuit 35 via a vertical signal line 41; see Par.[0309]-[0314] wherein the column signal processing circuit 35 is disposed at each column of the pixels 32 and performs signal processing such as noise removal on signals output from the pixels 32 corresponding to one row for each pixel column; the output circuit 37 performs signal processing on the signals sequentially supplied from the column signal processing circuits 35 via the horizontal signal line 42 and outputs the processed signals).
With respect to claim 7, Komai discloses, in Figs.1-119, the solid-state imaging device, wherein the substrate further includes: a first substrate, wherein the imaging element includes a photoelectric conversion unit, the photoelectric conversion unit is on the first substrate, and the photoelectric conversion unit is configured to perform the photoelectric conversion; and a second substrate on the first substrate, wherein the second substrate is configured to perform a signal processing operation on the electric signal that is photoelectrically converted by the photoelectric conversion unit, the first substrate includes: a signal output unit configured to; transmit a first signal to the imaging element and receive a second signal from the imaging element; and a conductive connection portion electrically connected to the signal output unit, the conductive connection portion extends to a side surface of the first substrate, the conductor is connected to the conductive connection portion, and the conductor is disposed on the side surface of the first substrate (see Par.[0307] wherein the pixel 32 includes a photodiode serving as a photoelectric conversion element and a plurality of pixel transistors; see Par.[0310]-[0311] wherein the pixel array unit 33 sequentially in units of rows in the vertical direction and supplies a pixel signal based on a signal charge generated according to an amount of light received in the photoelectric conversion portion of each pixel 32 to the column signal processing circuit 35 via a vertical signal line 41; see Par.[0309]-[0314] wherein the column signal processing circuit 35 is disposed at each column of the pixels 32 and performs signal processing such as noise removal on signals output from the pixels 32 corresponding to one row for each pixel column; the output circuit 37 performs signal processing on the signals sequentially supplied from the column signal processing circuits 35 via the horizontal signal line 42 and outputs the processed signals).
With respect to claim 8, Komai discloses, in Figs.1-119, the solid-state imaging device, wherein the substrate further includes: a first substrate (12), wherein in the imaging element (51) includes a photoelectric conversion unit, the photoelectric conversion unit is on the first substrate (12), and the photoelectric conversion unit is configured to perform the photoelectric conversion; and a second substrate (11) on the first substrate, wherein the second substrate is configured to perform a signal processing operation on the electric signal that is photoelectrically converted by the photoelectric conversion unit, the second substrate includes: a signal output unit configured to: transmit a first signal to the imaging element and receive a second signal from the imaging element; and the second substrate includes a conductive connection portion electrically connected to the signal output unit, the conductive connection portion extends to a side surface of the second substrate, the conductor is connected to the conductive connection portion, and the conductor is disposed on the side surface of the second substrate (see Par.[0307] wherein the pixel 32 includes a photodiode serving as a photoelectric conversion element and a plurality of pixel transistors; see Par.[0310]-[0311] wherein the pixel array unit 33 sequentially in units of rows in the vertical direction and supplies a pixel signal based on a signal charge generated according to an amount of light received in the photoelectric conversion portion of each pixel 32 to the column signal processing circuit 35 via a vertical signal line 41; see Par.[0309]-[0314] wherein the column signal processing circuit 35 is disposed at each column of the pixels 32 and performs signal processing such as noise removal on signals output from the pixels 32 corresponding to one row for each pixel column; the output circuit 37 performs signal processing on the signals sequentially supplied from the column signal processing circuits 35 via the horizontal signal line 42 and outputs the processed signals).
With respect to claim 9, Komai discloses, in Figs.1-119, the solid-state imaging device, wherein the conductor is on a plurality of side surfaces of the first substrate, the conductor is on a plurality of side surfaces of the second substrate, and the conductor is on a surface of the second substrate (see Fig.5).
With respect to claim 10, Komai discloses, in Figs.1-119, the solid-state imaging device, wherein the conductor is only on one of the second surface of the substrate or the side surface of the substrate (see Fig.5).
With respect to claim 11, Komai discloses, in Figs.1-119, the solid-state imaging device, wherein the conductor is continuous from the second surface of the substrate to the side surface of the substrate (see Fig.5).
With respect to claim 12, Komai discloses, in Figs.1-119, the solid-state imaging device, further comprising: a first set of conductors of a plurality of conductors that is on the second surface of the substrate and a second set of conductors of the plurality of conductors that is on the side surface of the substrate, wherein the first set of conductors is are provided separated from the second set of conductors each other, and one of the first set of conductors or the second set of conductors includes the conductor (see Fig.5).
With respect to claim 13, Komai discloses, in Figs.1-119, the solid-state imaging device, further comprising; a coupling portion on the at least one of the second surface of the substrate or the side surface of the substrate, wherein the coupling portion is configured to couple a plurality of conductors, the plurality of conductors includes the conductor, the substrate further includes a signal output unit, the plurality of conductors shares the signal output unit that is electrically connected to the plurality of conductors, and the signal output unit is configured to: transmit a first signal to the imaging element; and receive a second signal to and from the imaging element (see Par.[0309]-[0314] wherein a vertical synchronization signal, a horizontal synchronization signal, and a master clock, the control circuit 38 generates a clock signal or a control signal serving as a reference of operations of the vertical driving circuit 34, the column signal processing circuit 35, the horizontal driving circuit 36, and the like; the control circuit 38 outputs the generated clock signal or control signal to the vertical driving circuit 34, the column signal processing circuit 35, the horizontal driving circuit 36, and the like).
With respect to claim 14, Komai discloses, in Figs.1-119, the solid-state imaging device, further comprising; a coupling portion on the at least one of the second surface of the substrate or the side surface of the substrate, wherein the coupling portion is configured to couple a plurality of conductors, the plurality of conductors includes the conductor, wherein the substrate further includes a plurality of signal output units, the plurality of conductors coupled by the coupling portion is shared through the plurality of signal output units, the plurality of signal output units is electrically connected to the plurality of conductors, and each of the plurality of signal output units is configured to: transmit a first signal to the imaging element; and receive a second signal from the imaging element (see Par.[0309]-[0314] wherein a vertical synchronization signal, a horizontal synchronization signal, and a master clock, the control circuit 38 generates a clock signal or a control signal serving as a reference of operations of the vertical driving circuit 34, the column signal processing circuit 35, the horizontal driving circuit 36, and the like; the control circuit 38 outputs the generated clock signal or control signal to the vertical driving circuit 34, the column signal processing circuit 35, the horizontal driving circuit 36, and the like).
With respect to claim 15, Komai discloses, in Figs.1-119, the solid-state imaging device, wherein the conductor includes a single-layered conductive layer (see Fig.5).
With respect to claim 16, Komai discloses, in Figs.1-119, the solid-state imaging device, wherein the conductor includes a plurality of stacked conductive layers (see Fig.5).
With respect to claim 17, Komai discloses, in Figs.1-119, a manufacturing method for a solid state imaging device, the method comprising: forming, on a first surface/(upper surface) of a substrate (12), an imaging element (51), wherein the imaging element (51) generates an electric signal by photoelectric conversion of incident light/(light though lens 16) that is incident on the first surface/(upper surface) of the substrate (12) (see Par.[0342]-[0344] wherein the pixel sensor substrate 12, a multi-layer wiring layer 102 is formed on the lower side (the side of the logic substrate 11) of a semiconductor substrate 101 (hereinafter referred to as a silicon substrate 101) formed of a silicon (Si); see Par.[0318]-[0320] wherein the photodiode 51 is a photoelectric conversion portion that generates and accumulates a charge (signal charge) according to an amount of received light; it is submitted that received light cab only be through lens 16); and forming a conductor (106, 109, 103) on in surface contact with at least one of a second surface of the substrate (12) that is opposite to the first surface of the substrate (12), or a side surface of the substrate that is continuous with the second surface of the substrate (12), wherein the side surface of the substrate is electrically connected to the imaging element (see Par.[0344]-[0346] wherein the multi-layer wiring layer 102 includes a plurality of wiring layers 103 including an uppermost-layer wiring layer 103a closest to the silicon substrate 101; see Par.[0377] wherein the basic structure illustrated in FIG. 5. That is, the logic substrate 11 and the pixel sensor substrate 12 are connected to the upper side of the pixel sensor substrate 12 by using the connection wiring 106 and the two through electrodes, i.e., the silicon through electrode 109 and the chip through electrode 105; see Par.[0419]-[0420] wherein the silicon through electrode 109 and the chip through electrode 105).
With respect to claim 18, Komai discloses, in Figs.1-119, the manufacturing method for a solid-state imaging device, further comprising: forming a hole extending in a depth direction of the substrate from the second surface of the substrate, wherein the formation of the hole exposes a signal output unit, wherein the signal output unit: transmits a first signal to the imaging element; and receives a second signal from the imaging element; forming a contact member extending in the depth direction of the substrate and forming a metal layer from the second surface of the substrate so as to fill the hole, wherein the formation of the metal layer fills the hole, and the conductor is electrically connected to the contact member via the metal layer (see Par.[0344]-[0346] wherein the multi-layer wiring layer 102 includes a plurality of wiring layers 103 including an uppermost-layer wiring layer 103a closest to the silicon substrate 101; see Par.[0377] wherein the basic structure illustrated in FIG. 5. That is, the logic substrate 11 and the pixel sensor substrate 12 are connected to the upper side of the pixel sensor substrate 12 by using the connection wiring 106 and the two through electrodes, i.e., the silicon through electrode 109 and the chip through electrode 105; see Par.[0419]-[0420] wherein the silicon through electrode 109 and the chip through electrode 105).
With respect to claim 19, Komai discloses, in Figs.1-119, the manufacturing method for a solid state imaging device, further comprising: forming the imaging element on the first surface of the substrate before dividing the substrate into individual pieces; forming a conductive connection portion electrically connected to a signal output unit, wherein the signal output unit: transmits a first signal to the imaging element; and receives a second signal from the imaging element, and the conductive connection portion extends to a first region including a part of a dividing region for dividing the substrate into the individual pieces; forming, in the first region, a hole extending in a depth direction of the substrate from the second surface of the substrate, wherein the formation of the hole exposes the conductive connection portion; forming a metal layer from the second surface of the substrate the, wherein the formation of the metal layer fills the hole, and the filled hole electrically connects the conductor to the conductive connection portion; and dividing the substrate into the individual pieces along the dividing region (see Par.[0309]-[0314] wherein a vertical synchronization signal, a horizontal synchronization signal, and a master clock, the control circuit 38 generates a clock signal or a control signal serving as a reference of operations of the vertical driving circuit 34, the column signal processing circuit 35, the horizontal driving circuit 36, and the like; the control circuit 38 outputs the generated clock signal or control signal to the vertical driving circuit 34, the column signal processing circuit 35, the horizontal driving circuit 36, and the like).
With respect to claim 20, Komai discloses, in Figs.1-119, the manufacturing method for a solid state imaging device, further comprising: forming the imaging element on the first surface of the substrate before dividing the substrate into individual pieces; forming a sacrificial layer (412) extending to a first region including a part of a dividing region for dividing the substrate (12) into the individual pieces; forming, in the first region, a hole (414) extending in a depth direction of the substrate from the second surface of the substrate (12), wherein the formation of the hole exposes the sacrificial layer (see Fig.22, Par.[0436] wherein as illustrated in FIG. 22, a resist 412 is applied to the insulation film 108, the resist 412 is patterned in accordance with the regions in which the silicon through electrode 109 and the chip through electrode 105 are formed, and openings 413 and 414 corresponding to the chip through electrode 105 and the silicon through electrode 109 are formed); removing the sacrificial layer (see Fig.23, Par.[0437] wherein as illustrated in FIG. 23, after insulation films 107 are formed on the inner walls of the openings 413 and 414 by a plasma CVD method, the insulation films 107 of the bottom portions of the openings 413 and 414 are removed by an etch-back method); forming, in a region where the sacrificial layer (412) is removed, a conductive connection portion electrically connected to a signal output unit, wherein the signal output unit: configured to transmits and receive a first signal to and from the imaging element; and receives a second signal from the imaging element; forming a metal layer from the second surface of the substrate so as to fill the hole, wherein the formation of the metal layer fills the hole, and the filled hole electrically connects to form the conductor electrically connected to the conductive connection portion; and dividing the substrate into the individual pieces along the dividing region (see Par.[0309]-[0314] wherein a vertical synchronization signal, a horizontal synchronization signal, and a master clock, the control circuit 38 generates a clock signal or a control signal serving as a reference of operations of the vertical driving circuit 34, the column signal processing circuit 35, the horizontal driving circuit 36, and the like; the control circuit 38 outputs the generated clock signal or control signal to the vertical driving circuit 34, the column signal processing circuit 35, the horizontal driving circuit 36, and the like).
Response to Arguments
Applicant’s arguments with respect to claims 1 and 17 have been considered but are moot because the current of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Citation of Pertinent Prior Art
The prior art made of record (e.g.; see PTO-892) and not relied upon is considered pertinent to applicant's disclosure.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Examiner’s Telephone/Fax Contacts
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MOULOUCOULAYE INOUSSA whose telephone number is (571)272-0596. The examiner can normally be reached Monday-Friday (10-18).
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, JEFF W NATALINI can be reached at 571-272-2266. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/Mouloucoulaye Inoussa/ Primary Examiner, Art Unit 2818
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