Prosecution Insights
Last updated: April 19, 2026
Application No. 18/546,693

CONNECTION STRUCTURE, DISPLAY PANEL, MANUFACTURING METHOD, DETECTION CIRCUITRY, AND DISPLAY DEVICE

Non-Final OA §103
Filed
Aug 16, 2023
Examiner
NADAV, ORI
Art Unit
2811
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
BOE TECHNOLOGY GROUP CO., LTD.
OA Round
1 (Non-Final)
60%
Grant Probability
Moderate
1-2
OA Rounds
3y 11m
To Grant
81%
With Interview

Examiner Intelligence

Grants 60% of resolved cases
60%
Career Allow Rate
417 granted / 693 resolved
-7.8% vs TC avg
Strong +21% interview lift
Without
With
+20.6%
Interview Lift
resolved cases with interview
Typical timeline
3y 11m
Avg Prosecution
67 currently pending
Career history
760
Total Applications
across all art units

Statute-Specific Performance

§101
0.4%
-39.6% vs TC avg
§103
52.6%
+12.6% vs TC avg
§102
14.2%
-25.8% vs TC avg
§112
29.5%
-10.5% vs TC avg
Black line = Tech Center average estimate • Based on career data from 693 resolved cases

Office Action

§103
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . DETAILED ACTION Election/Restrictions Applicant’s election of the embodiment of a connection structure and device claims in the reply filed on 12/24/2025 is acknowledged. Because applicant did not distinctly and specifically point out the supposed errors in the restriction requirement, the election has been treated as an election without traverse (MPEP § 818.01(a)). Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claims 1-15 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Cai (11,257,888) in view of Jin et al. (2019/0140202).Regarding claims 1, 12, 13 and 20, Cai et al. teach in figure 9 and related text a display device, comprising the display panel a comprising the display substrate comprising a connection structure electrically coupled to an input pin of a display driver integrated circuitry, comprising a connection unit, (the entire structure) wherein the connection unit comprises a first connection member (the top part), a second connection member (the bottom part), and a binding member (un-depicted, see figure 1) arranged on a base substrate 10; wherein the first connection member comprises a plurality of first connectors 80, the second connection member comprises a plurality of second connectors 30, 60, the binding member comprises a plurality of binding pins (see figure 1), the input pin is electrically coupled to the second connector through the first connector, the second connector is electrically coupled to the binding pin, the connection unit comprises a plurality of metal layers 30, 60, 80 and a plurality of insulation layers 20, 70, 90, the second connector comprises a second connection line, the second connection line comprises at least two second connection line portions electrically coupled to each other, the at least two second connection line portions are formed by at least two metal layers (portions of elements 30 and 60) in the plurality of metal layers respectively, and at least two insulation layers 20, 70 in the connection unit are arranged on a side of the at least two metal layers away from the base substrate. Cai et al. do not explicitly state using a binding member comprises a plurality of binding pins. Jin et al. teach in figure 19 and related text using a binding member B22 comprises a plurality of binding pins. Jin et al. and Cai et al. are analogous art because they are directed to display devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify Cai et al. because they are from the same field of endeavor.It would have been obvious to a person of ordinary skill in the art, before the effective filling date of the claimed invention, to use a binding member comprises a plurality of binding pins, as taught by Jin et al., in Cai et al.’s device, in order to be able to operate the device by using external connections. Regarding claim 2, Cai et al. teach in figure 9 and related text that the first connector 80 comprises a first connection line, the first connection line comprises at least two first connection line portions (vertical and horizontal portions) electrically coupled to each other, the at least two first connection line portions are formed by at least two metal layers of the plurality of metal layers respectively, and the first connection line is electrically coupled to the second connection line. Regarding claim 3, Cai et al. teach in figure 9 and related text that the first connection line further comprises at least one first connection line portion, and all the first connection line portions of the first connection line are electrically coupled to each other, and the at least one first connection line portion is formed by at least one metal layer in the plurality of metal layers other than the at least two metal layers. Regarding claim 4, Cai et al. teach in figure 9 and related text that the connection unit comprises a first metal layer 30, a first insulation layer 20, a second metal layer 60, a second insulation layer 70, a third metal layer80 and a third insulation layer 90 arranged one on another along a direction away from the base substrate, the second connection line comprises a first one of second connection line portions and a second one of second connection line portions electrically coupled to each other, the first one of second connection line portions is formed by the first metal layer, and the second one of second connection line portions is formed by the second metal layer. Regarding claim 5, Cai et al. do not teach that a thickness of the first insulation layer is greater than 3000 angstroms and less than or equal to 4000 angstroms, a thickness of the second insulation layer is greater than or equal to 4000 angstroms and less than or equal to 6000 angstroms, and a thickness of the third insulation layer is greater than or equal to 600 angstroms and less than or equal to 2000 angstroms. It would have been obvious to a person of ordinary skill in the art, before the effective filling date of the claimed invention, to form a thickness of the first insulation layer is greater than 3000 angstroms and less than or equal to 4000 angstroms, a thickness of the second insulation layer is greater than or equal to 4000 angstroms and less than or equal to 6000 angstroms, and a thickness of the third insulation layer is greater than or equal to 600 angstroms and less than or equal to 2000 angstroms in prior art’s device in order to adjust the device characteristics according to the requirements of the application at hand. Regarding claim 6, Cai et al. teach in figure 9 and related text that the first connector comprises a first connection line, the first connection line comprises a first one of first connection line portions and a second one of first connection line portions electrically coupled to each other, the first one of first connection line portions is formed by the first metal layer, the second one of first connection line portions is formed by the second metal layer, the first one of first connection line portions is electrically coupled to the first one of second connection line portions, and the second one of first connection line portions is electrically coupled to the second one of second connection line portions. Regarding claim 7, Cai et al. teach in figure 9 and related text that the first connection line further comprises a third one of first connection line portions (arbitrarily chosen), the third one of first connection line portions is electrically coupled to the first one of first connection line portions and the second one of first connection line portions, and the third one of first connection line portions is formed by the third metal layer. Regarding claim 8, Cai et al. teach in figure 9 and related text that the first metal layer is a shielding layer 30, the second metal layer is a gate metal layer 60, and the third metal layer is a source/drain metal layer 80. Regarding claim 9, Cai et al. teach in figure 9 and related text that the first insulation layer comprises a buffer layer 20 and a gate insulation layer 50 arranged one on another along a direction away from the base substrate, the second insulation layer is an interlayer dielectric layer 70, and the third insulation layer is a passivation layer 90. Regarding claim 10, Jin et al. teach in figure 19 and related text that the binding pin B22 comprises a binding connection line electrically coupled to the second connection line and comprising a first binding connection line portion 197 and a second binding connection line portion (another 197) electrically coupled to each other. Prior art does not explicitly state that the first binding connection line portion is formed by the second metal layer, and the second binding connection line portion is formed by the third metal layer. It would have been obvious to a person of ordinary skill in the art, before the effective filling date of the claimed invention, to form the first binding connection line portion by the second metal layer, and the second binding connection line portion by the third metal layer, in prior art’s device in order to simplify the processing steps of making adjust the device. Regarding claim 11, Jin et al. teach in figure 19 and related text that an extension direction of the binding pin is a first direction, but does not teach that a length of the second connector along the first direction is greater than 0.07 mm and less than or equal to 0.09 mm. It would have been obvious to a person of ordinary skill in the art, before the effective filling date of the claimed invention, to form a length of the second connector along the first direction is greater than 0.07 mm and less than or equal to 0.09 mm in prior art’s device in order to adjust the device characteristics according to the requirements of the application at hand. Regarding claim 14, Jin et al. teach in figure 19, and thus prior art, a flexible circuitry board, wherein pins of the flexible circuitry board are bound to binding pins. Regarding claim 15, prior art does not teach that a distance between a first edge of each pin of the flexible circuitry board and a cutting edge of the flexible circuitry board is greater than or equal to 10 m and less than or equal to 30 m, the first edge is an edge of the pin close to the cutting edge, and the cutting edge is an edge of the flexible circuitry board closest to the first connection member. It would have been obvious to a person of ordinary skill in the art, before the effective filling date of the claimed invention, to form a distance between a first edge of each pin of the flexible circuitry board and a cutting edge of the flexible circuitry board is greater than or equal to 10 m and less than or equal to 30 m, the first edge is an edge of the pin close to the cutting edge, and the cutting edge is an edge of the flexible circuitry board closest to the first connection member, in prior art’s device in order to adjust the device characteristics according to the requirements of the application at hand. Any inquiry concerning this communication or earlier communications from the examiner should be directed to ORI NADAV whose telephone number is 571-272-1660. The examiner can normally be reached between the hours of 7 AM to 4 PM (Eastern Standard Time) Monday through Friday. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Lynne Gurley can be reached on 571-272-1670. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). O.N. /ORI NADAV/ 2/6/2026 PRIMARY EXAMINER TECHNOLOGY CENTER 2800
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Prosecution Timeline

Aug 16, 2023
Application Filed
Jan 22, 2026
Non-Final Rejection — §103 (current)

Precedent Cases

Applications granted by this same examiner with similar technology

Patent 12599028
SEMICONDUCTOR PACKAGES HAVING ADHESIVE MEMBERS
2y 5m to grant Granted Apr 07, 2026
Patent 12588281
DISPLAY APPARATUS COMPRISING THIN FILM TRANSISTOR
2y 5m to grant Granted Mar 24, 2026
Patent 12581995
Light Emitting Display Panel
2y 5m to grant Granted Mar 17, 2026
Patent 12566097
USE OF A SPIN TRANSITION MATERIAL TO MEASURE AND/OR LIMIT THE TEMPERATURE OF ELECTRONIC/PHOTONIC COMPONENTS
2y 5m to grant Granted Mar 03, 2026
Patent 12543452
DISPLAY DEVICE
2y 5m to grant Granted Feb 03, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
60%
Grant Probability
81%
With Interview (+20.6%)
3y 11m
Median Time to Grant
Low
PTA Risk
Based on 693 resolved cases by this examiner. Grant probability derived from career allow rate.

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