tice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Election/Restrictions Applicant’s election without traverse of group IV in the reply filed on March 26, 2026 is acknowledged. Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale , or otherwise available to the public before the effective filing date of the claimed invention. Claim s 1 , 15, 17-19, 21-25 are rejected under 35 U.S.C. 102 (a)(1) as being anticipated by Yoo (US 2018/0240803) . Regarding claim 1 , Yoo discloses a ferroelectric field-effect transistor comprising: a substrate (101) [Fig. 1] ; a source (102) disposed over a first region of the substrate [Fig. 1] ; a drain (103) disposed over a second region of the substrate, wherein the second region is spaced apart from the first region [Fig. 1] ; a channel (region between source and drain) comprised of a semiconductor material within a third region that is between the first region and the second region [Fig. 1] ; and a gate stack comprising: an interfacial layer (115) disposed over the channel, wherein the interfacial layer has a permittivity that is greater than 3.9 (e.g. silicon nitride) [Fig. 1 and paragraph 0024] ; and a layer of ferroelectric material (125) disposed over the interfacial layer [Fig. 1 and paragraph 0025] . Regarding claim 15 , Yoo discloses wherein the channel comprises a crystalline, poly-crystalline, or amorphous form of two-dimensional semiconductors [Fig. 1 and paragraph 0022] . Regarding claim 17 , Yoo discloses wherein the interfacial layer (115) has a permittivity that is larger than 4 (e.g. silicon nitride) [paragraph 0024] . Regarding claim 18 , Yoo discloses wherein the interfacial layer (115) comprises high permittivity (k>4) insulators (e.g. silicon nitride , oxynitride ) [paragraph 0024]. Regarding claim 19 , Yoo discloses wherein the high permittivity (k>4) insulators comprise silicon nitride, hafnium oxide, zirconium oxide, silicon- oxynitride, hafnium oxynitride, zirconium oxynitride, lanthanum oxide, other doped binary oxides, and combinations thereof [paragraph 0024] . Regarding claim 21 , Yoo discloses wherein the ferroelectric material (125) comprises a binary material [paragraph 0025-0026] . Regarding claim 22 , Yoo discloses wherein the binary material is hafnium oxide [paragraph 0025-0026]. Regarding claim 23 , Yoo discloses wherein the hafnium oxide is zirconium dopedzirconium -doped [paragraph 0025-0026]. Regarding claim 24 , Yoo discloses wherein the hafnium oxide is doped with a dopant atom [paragraph 0025-0026]. Regarding claim 25 , Yoo discloses wherein the dopant atom is from the group consisting of aluminum, yttrium, and silicon [paragraph 0025-0026]. Regarding claim 29 , Yoo discloses a method of fabricating a ferroelectric field-effect transistor comprising: providing a substrate ( 101) [Fig. 1] ; disposing a source (102) over a first region of the substrate [Fig. 1] ; disposing a drain (103) over a second region of the substrate, wherein the second region is spaced apart from the first region forming a channel between the source and the drain [Fig. 1] ; forming a gate stack by: disposing an interfacial layer (115) over the channel, wherein the interfacial layer has a permittivity that is greater than 3.9 [Fig. 1 and paragraph 0024] ; and disposing a layer of ferroelectric material (125) over the interfacial layer ]Fig. 1 and paragraph 0025-0026] . Regarding claim 31 , Yoo discloses wherein the interfacial layer has a permittivity that is larger than 4.0 (e.g. silicon nitride) [paragraph 0024]. Regarding claim 33 , Yoo discloses wherein the ferroelectric material (125) comprises a binary material [paragraph 0025-0026]. Regarding claim 34 , Yoo discloses wherein the binary material is hafnium oxide [paragraph 0025-0026]. Regarding claim 35 , Yoo discloses wherein the hafnium oxide is zirconium-doped [paragraph 0025-0026]. Regarding claim 51 , Yoo discloses wherein the channel comprises a crystalline, poly-crystalline, or amorphous form of two-dimensional semiconductors [paragraph 0022] . Regarding claim 53 , Yoo discloses wherein the interfacial layer (115) comprises high permittivity (k>4) insulators [paragraph 0024] . Regarding claim 54 , Yoo discloses wherein the high permittivity (k>4) insulators comprise silicon nitride, hafnium oxide, silicon-oxynitride, hafnium oxynitride, lanthanum oxide, doped binary oxides, and combinations thereof [paragraph 0024] . Claim s 1 , 15,17-19, 21-25. 17, 29, 31-35, 37, 51 and 53-54 are rejected under 35 U.S.C. 102 (a)(1) as being anticipated by Young et al. (US 2020/0176585 ) . Regarding claim 1 , Young discloses a ferroelectric field-effect transistor comprising: a substrate ( 202 ) [Fig. 1 6 ] ; a source ( 224 ) disposed over a first region of the substrate [Fig. 1 6 ] ; a drain ( 224 ) disposed over a second region of the substrate, wherein the second region is spaced apart from the first region [Fig. 1 6 ] ; a channel ( 204/ 206 ) comprised of a semiconductor material within a third region that is between the first region and the second region [Fig. 1 6 ] ; and a gate stack comprising: an interfacial layer ( 230 ) disposed over the channel, wherein the interfacial layer has a permittivity that is greater than 3.9 (e.g. silicon nitride) [Fig. 1 6 and paragraph 00 34 ] ; and a layer of ferroelectric material ( 232 ) disposed over the interfacial layer [Fig. 1 6 and paragraph 00 34 ] . Regarding claim 15, Young discloses wherein the channel comprises a crystalline, poly-crystalline, or amorphous form of two-dimensional semiconductors [Fig. 1 6 and paragraph 0017 ]. Regarding claim 17, Young discloses wherein the interfacial layer ( 230 ) has a permittivity that is larger than 4 (e.g. silicon nitride) [paragraph 00 3 4]. Regarding claim 18, Young discloses wherein the interfacial layer ( 230 ) comprises high permittivity (k>4) insulators (e.g. silicon nitride, oxynitride) [paragraph 00 3 4]. Regarding claim 19, Young discloses wherein the high permittivity (k>4) insulators comprise silicon nitride, hafnium oxide, zirconium oxide, silicon- oxynitride, hafnium oxynitride, zirconium oxynitride, lanthanum oxide, other doped binary oxides, and combinations thereof [paragraph 00 3 4]. Regarding claim 21, Young discloses wherein the ferroelectric material ( 232 ) comprises a binary material [paragraph 0035 ]. Regarding claim 22, Young discloses wherein the binary material is hafnium oxide [paragraph 0035 ]. Regarding claim 23, Young discloses wherein the hafnium oxide is zirconium doped zirconium-doped [paragraph 0035 ]. Regarding claim 24, Young discloses wherein the hafnium oxide is doped with a dopant atom [paragraph 0035 ]. Regarding claim 25, Young discloses wherein the dopant atom is from the group consisting of aluminum, yttrium, and silicon [paragraph 0035 ]. Regarding claim 27 , Young discloses wherein the ferroelectric material comprises a perovskite ferroelectric material [paragraph 0035] . Regarding claim 29, Young discloses a method of fabricating a ferroelectric field-effect transistor comprising: providing a substrate ( 202 ) [Fig. 1 6 ]; disposing a source ( 224 ) over a first region of the substrate [Fig s . 10-11 and 1 6 ]; disposing a drain ( 224 ) over a second region of the substrate, wherein the second region is spaced apart from the first region forming a channel (204/206) between the source and the drain [Fig. 1 0-11 and 16 ]; forming a gate stack by: disposing an interfacial layer ( 230 ) over the channel, wherein the interfacial layer has a permittivity that is greater than 3.9 [Fig. 1 6 and paragraph 00 3 4]; and disposing a layer of ferroelectric material ( 232 ) over the interfacial layer [ Fig. 1 6 and paragraph 0035 ]. Regarding claim 31, Young discloses wherein the interfacial layer has a permittivity that is larger than 4.0 (e.g. silicon nitride) [paragraph 0034 ]. Regarding claim 32 , Young discloses wherein disposing the interfacial layer (230) comprises thermally growing silicon nitride onto the channel [paragraph 0034] . Regarding claim 33, Young discloses wherein the ferroelectric material ( 232 ) comprises a binary material [paragraph 0035 ]. Regarding claim 34, Young discloses wherein the binary material is hafnium oxide [paragraph 0035 ]. Regarding claim 35, Young discloses wherein the hafnium oxide is zirconium-doped [paragraph 0035 ]. Regarding claim 37 , Young discloses wherein the ferroelectric material (232) comprises a perovskite material [paragraph 0035] . Regarding claim 51, Young discloses wherein the channel comprises a crystalline, poly-crystalline, or amorphous form of two-dimensional semiconductors [paragraph 0017 ]. Regarding claim 53, Young discloses wherein the interfacial layer ( 230 ) comprises high permittivity (k>4) insulators [paragraph 00 3 4]. Regarding claim 54, Young discloses wherein the high permittivity (k>4) insulators comprise silicon nitride, hafnium oxide, silicon-oxynitride, hafnium oxynitride, lanthanum oxide, doped binary oxides, and combinations thereof [paragraph 00 3 4]. Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim s 26 , 28, 36 and 38 are rejected under 35 U.S.C. 103 as being unpatentable over Young et al. (US 2020/0176585) in view of Vellianitis (US 2021/0391471) . Regarding claims 26 and 36, Young does not teach binary material is scandium nitride . However, Vellianitis teaches scandium nitride is a well-known ferroelectric material [paragraph 0012]. Therefore, one of ordinary skill in the art, before the effective filing date of the claimed invention, would have been motivated to modify Young by including scandium nitride as the ferroelectric material as taught by Vellianitis because helps to increase the piezoelectric effect [paragraph 0012] . Regarding claims 28 and 38, Young , as stated before, teaches the same claimed the interfacial material [See paragraph 0034]. Hence, it is assumed that the interface in Young also provide an endurance of greater than 1012 cycles. Claim s 16 and 52 are rejected under 35 U.S.C. 103 as being unpatentable over Young et al. (US 2020/0176585) in view of Van Houdt et al. (US 2017/0040331 ) . Regarding claims 16 and 52, Young does not teach the two- dimensional semiconductors are chalcogenides . Van Houdt et al. teaches the two- dimensional semiconductors are chalcogenides [paragraphs 0033-0036]. Therefore, one of ordinary skill in the art, before the effective filing date of the claimed invention, would have been motivated to modify Young by including scandium nitride as the ferroelectric material as taught by Van Houdt because helps to the transistor performance [paragraph 0033-0034 ]. Allowable Subject Matter Claims 20 and 55 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to FILLIN "Examiner name" \* MERGEFORMAT JOSE R DIAZ whose telephone number is FILLIN "Phone number" \* MERGEFORMAT (571)272-1727 . The examiner can normally be reached FILLIN "Work Schedule?" \* MERGEFORMAT Monday-Friday . Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, FILLIN "SPE Name?" \* MERGEFORMAT Joshua Benitez can be reached at FILLIN "SPE Phone?" \* MERGEFORMAT 571-270-1435 . The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /Jose R Diaz/ Primary Examiner, Art Unit 2815