Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 4 and 8 rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, because the specification, while being enabling for “titanium (Ti), niobium (Nb), platinum (Pt), gold (Au) or the like”, does not reasonably provide enablement for all electrode material excluding aluminum. The specification does not enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make the invention commensurate in scope with these claims.
The broadest reasonable interpretation of claims 4 and 8 covers a method for manufacturing a device where the electrode material isn’t aluminum. The specification discloses enough information for one of ordinary skill in the art to make a device where the electrode material is “titanium, niobium, platinum, and gold, or a combination of two or more thereof “ (Par. 76 of specification). The specification does not provide an exhaustive list of electrode materials that exclude aluminum. An example of a material outside the scope of enablement is cobalt silicide. Cobalt silicide is a material that excludes aluminum that is suitable for use as a material for a source/drain electrode. Thus, the disclosed example does not bear a reasonable correlation to the full scope of the claim. Taking these factors into account, undue experimentation would be required by one of ordinary skill in the art to practice the full scope of claims 4 and 8.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-10 are rejected under 35 U.S.C. 103 as being unpatentable over Hayashida et al. (US20190058040A1, hereinafter Hayashida) in view of Harada et al. (US5350709A, hereinafter Harada).
Regarding claim 1, Hayashida teaches a method for manufacturing a semiconductor device comprising:
ion-implanting impurities into a source-drain electrodes forming region (Par. 94 “the n-type contact layer 12 is preferably formed through donor impurity implantation”) where a source electrode and a drain electrode are to be formed on a nitride semiconductor layer formed on a substrate (Par. 64 “n-type contact layer 12 is disposed on the top surface ST of the stack 51, and …[t]he source electrode portion 14 is in contact with the n-type contact layer 12”);
forming a silicon nitride film on the surface of the nitride semiconductor layer and the silicon nitride film constituting a surface protecting sacrifice film having a thickness of 100 nm or more and 500 nm or less (Fig. 14 insulating films 11 and 13. Par. 117 teaches that insulating film 11 is a “SiN film having a thickness of about 30 nm” and par. 122 teaches that insulating film 13 is “a SiN film…[with a] thickness of about 100 nm” and so the thickness lies within the claimed range, see MPEP 2144.05(I)); and
heat-treating the nitride semiconductor layer on which the surface protecting sacrifice film is formed (Par. 118 “The n-type contact layer 12, which functions as a contact layer, is preferably doped at a high concentration“ and “a dopant undergoes heating at a temperature of about 1100° C. to 1200° C. for activation” which constitutes a heat treatment).
Hayashida does not appear to teach
forming a silicon nitride film on the surface of the nitride semiconductor layer by a plasma-enhanced chemical vapor deposition method; and
the silicon nitride film having a refractive index of 1.80 or more and less than 1.88.
Harada teaches
forming a silicon nitride film on the surface of the nitride semiconductor layer by a plasma-enhanced chemical vapor deposition method (Col. 8 lines 60-63 “[t]he SiOx/SiN composite film is formed using a conventional plasma-enhanced chemical vapor deposition (P-CVD) process”); and
the silicon nitride film having a refractive index of 1.80 or more and less than 1.88 (Col. 10 lines 3-15 “if the refractive index of the SiN film formed by plasma CVD is greater than 1.9” then “the ability to prevent the external diffusion of As” decreases. Therefore, as refractive index of a PECVD deposited layer affects its ability to prevent external diffusion, it is a result effective variable that may be optimized by a person of ordinary skill, see MPEP 2144.05(II)(B). Examiner additionally notes that Harada explicitly teaches “deposition conditions for the SiN film [such that]…the refractive index was 1.8”).
Being in analogous arts, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention because as both Hayashida and Harada teach a suitable method for forming a SiN film, it would have been obvious to substitute Hayashida’s sputtering deposition with Harada’s PECVD deposition to achieve the predictable result of using PECVD to form a SiN film. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to further modify Hayashida with the teachings of Harada in order to ensure that excessive out diffusion does not occur.
Regarding claim 2, Hayashida teaches a method for manufacturing a semiconductor device comprising:
ion-implanting impurities into a source-drain electrodes forming region (Par. 94 “the n-type contact layer 12 is preferably formed through donor impurity implantation”) where a source electrode and a drain electrode are to be formed on a nitride semiconductor layer formed on a substrate (Par. 64 “n-type contact layer 12 is disposed on the top surface ST of the stack 51, and …[t]he source electrode portion 14 is in contact with the n-type contact layer 12”);
forming a silicon nitride film on the surface of the nitride semiconductor layer, the silicon nitride film constituting a lower surface protecting sacrifice film which is one layer of a surface protecting sacrifice film including two layers of an upper surface protecting sacrifice film and the lower surface protecting sacrifice film (Fig. 14 insulating films 11 and 13 both comprise SiN and so comprise a single SiN film with a lower surface protecting film 11 and upper surface protecting film 13), the lower surface protecting sacrifice film having a thickness of 30 nm or more (Par. 117 teaches that insulating film 11 is a “SiN film having a thickness of about 30 nm”);
forming the upper surface protecting sacrifice film stacked on the lower surface protecting sacrifice film and having a total thickness of 100 nm or more and 500 nm or less with the lower surface protecting sacrifice film (Par. 122 teaches that insulating film 13 is “a SiN film…[with a] thickness of about 100 nm” and so the total thickness of 130 nm lies within the claimed range, see MPEP 2144.05(I)); and
heat-treating the nitride semiconductor layer on which the surface protecting sacrifice film is formed (Par. 118 “The n-type contact layer 12, which functions as a contact layer, is preferably doped at a high concentration“ and “a dopant undergoes heating at a temperature of about 1100° C. to 1200° C. for activation” which constitutes a heat treatment).
Hayashida does not appear to teach
forming a silicon nitride film on the surface of the nitride semiconductor layer by a plasma-enhanced chemical vapor deposition method; and
the lower surface protecting sacrifice film having a refractive index of 1.80 or more and less than 1.88.
Harada teaches
forming a silicon nitride film on the surface of the nitride semiconductor layer by a plasma-enhanced chemical vapor deposition method (Col. 8 lines 60-63 “[t]he SiOx/SiN composite film is formed using a conventional plasma-enhanced chemical vapor deposition (P-CVD) process”); and
the silicon nitride film having a refractive index of 1.80 or more and less than 1.88 (Col. 10 lines 3-15 “if the refractive index of the SiN film formed by plasma CVD is greater than 1.9” then “the ability to prevent the external diffusion of As” decreases. Therefore, as refractive index of a PECVD deposited layer affects its ability to prevent external diffusion, it is a result effective variable that may be optimized by a person of ordinary skill, see MPEP 2144.05(II)(B). Examiner additionally notes that Harada explicitly teaches “deposition conditions for the SiN film [such that]…the refractive index was 1.8”).
Being in analogous arts, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention because as both Hayashida and Harada teach a suitable method for forming a SiN film, it would have been obvious to substitute Hayashida’s sputtering deposition with Harada’s PECVD deposition to achieve the predictable result of using PECVD to form a SiN film. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to further modify Hayashida with the teachings of Harada in order to ensure that excessive out diffusion does not occur.
Regarding claim 3, the combination of Hayashida and Harada teaches the method for manufacturing a semiconductor device according to claim 1,
wherein a heat treatment temperature during heat treatment is 1000 0C or more and 1200 °C or less (Hayashida par. 118 “[t]he n-type contact layer 12, which functions as a contact layer, is preferably doped at a high concentration“ and “a dopant undergoes heating at a temperature of about 1100° C. to 1200° C. for activation” which lies in the claimed range, see MPEP 2144.05(I)).
Regarding claim 4, the combination of Hayashida and Harada teaches the method for manufacturing a semiconductor device according to claim 1,
wherein the source electrode and the drain electrode are made of an electrode material excluding aluminum (Hayashida fig. 14, par. 127 source electrode portion 14 is made from “a stacked film made of metals, such as titanium (Ti)” which examiner notes isn’t aluminum).
Regarding claim 5, the combination of Hayashida and Harada teaches the method for manufacturing a semiconductor device according to claim 1,
wherein the electrode material is any one of titanium, niobium, platinum, and gold, or a combination of two or more thereof (Hayashida fig. 14, par. 127 source electrode portion 14 is made from “a stacked film made of metals, such as titanium (Ti)”).
Regarding claim 6, the combination of Hayashida and Harada teaches the method for manufacturing a semiconductor device according to claim 1,
wherein the surface protecting sacrifice film is removed by wet etching (Hayashida par. 125 “the insulating film 13 and the insulating film 11 have been formed of SiN films” and so “a hot phosphoric acid is used as an etchant” which constitutes a wet etch).
Regarding claim 7, the combination of Hayashida and Harada teaches the method for manufacturing a semiconductor device according to claim 2,
wherein a heat treatment temperature during heat treatment is 1000 °C or more and 1200 °C or less (Hayashida par. 118 “[t]he n-type contact layer 12, which functions as a contact layer, is preferably doped at a high concentration“ and “a dopant undergoes heating at a temperature of about 1100° C. to 1200° C. for activation” which lies in the claimed range, see MPEP 2144.05(I)).
Regarding claim 8, the combination of Hayashida and Harada teaches the method for manufacturing a semiconductor device according to claim 2,
wherein the source electrode and the drain electrode are made of an electrode material excluding aluminum (Hayashida fig. 14, par. 127 source electrode portion 14 is made from “a stacked film made of metals, such as titanium (Ti)” which examiner notes isn’t aluminum).
Regarding claim 9, the combination of Hayashida and Harada teaches the method for manufacturing a semiconductor device according to claim 2,
wherein the electrode material is any one of titanium, niobium, platinum, and gold, or a combination of two or more thereof (Hayashida fig. 14, par. 127 source electrode portion 14 is made from “a stacked film made of metals, such as titanium (Ti)”).
Regarding claim 10, the combination of Hayashida and Harada teaches the method for manufacturing a semiconductor device according to claim 2,
wherein the surface protecting sacrifice film is removed by wet etching (Hayashida par. 125 “the insulating film 13 and the insulating film 11 have been formed of SiN films” and so “a hot phosphoric acid is used as an etchant” which constitutes a wet etch).
Conclusion
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/COLE LEON LINDSEY/Examiner, Art Unit 2812 /CHRISTINE S. KIM/Supervisory Patent Examiner, Art Unit 2812