Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s arguments, see section titled “Rejection Under 35 U.S.C. 112,” filed 04/20/2026, with respect to the rejection of claims 4 and 8 under 35 U.S.C. 112 have been fully considered and are persuasive. The rejection of claims 4 and 8 under 35 U.S.C. 112 has been withdrawn.
Applicant’s arguments, see section titled “Rejection Under 35 U.S.C. 103,” filed 04/20/2026, with respect to the rejection(s) of claim(s) 1-10 under 35 U.S.C. 103 have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of Nishimori et al. (US20160343843A1, hereinafter Nishimori) in view of Harada et al. (US5350709A, hereinafter Harada).
Regarding amended claim 1, Nishimori (US20160343843A1) teaches a method for manufacturing a semiconductor device comprising:
ion-implanting impurities into a source-drain electrodes forming region where a source electrode and a drain electrode are to be formed on a nitride semiconductor layer formed on a substrate (Par. 42 “ion implantation is applied with an impurity element such as Si to regions 920 b where n-type regions 920 a are to be formed in the electron supply layer 922 and the electron transit layer 921 immediately below regions where a source electrode 942 and a drain electrode 943 are to be formed”);
forming a silicon nitride film on the surface of the nitride semiconductor layer, the silicon nitride film constituting a surface protecting sacrifice film and a thickness of 100 nm or more and 500 nm or less (Par. 43 “as illustrated in FIG. 2C, a heat-protective film 931 is formed of SiN with the thickness of about 200 nm on the electron supply layer 922”);
heat-treating the nitride semiconductor layer on which the surface protecting sacrifice film is formed (Par. 44 “as illustrated in FIG. 3A…RTA (Rapid Thermal Annealing) is performed”); and
removing the surface protecting sacrifice film (Par. 45 “as illustrated in FIG. 3B, the heat-protective film 931 is removed by using a solvent that includes hydrofluoric acid”).
Nishimori does not appear to teach
forming a silicon nitride film on the surface of the nitride semiconductor layer by a plasma- enhanced chemical vapor deposition method; and
the silicon nitride film having a refractive index of 1.80 or more and less than 1.88.
Harada teaches
forming a silicon nitride film on the surface of the nitride semiconductor layer by a plasma-enhanced chemical vapor deposition method (Col. 8 lines 60-63 “[t]he SiOx/SiN composite film is formed using a conventional plasma-enhanced chemical vapor deposition (P-CVD) process”); and
the silicon nitride film having a refractive index of 1.80 or more and less than 1.88 (Col. 10 lines 3-15 “if the refractive index of the SiN film formed by plasma CVD is greater than 1.9” then “the ability to prevent the external diffusion of As” decreases. Therefore, as refractive index of a PECVD deposited layer affects its ability to prevent external diffusion, it is a result effective variable that may be optimized by a person of ordinary skill, see MPEP 2144.05(II)(B). Examiner additionally notes that Harada explicitly teaches “deposition conditions for the SiN film [such that]…the refractive index was 1.8”).
Being in analogous arts, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Nishimori with the teachings of Harada because as both Nishimori and Harada teach a suitable method for forming a SiN film, it would have been obvious to substitute Nishimori’s CVD deposition with Harada’s PECVD deposition to achieve the predictable result of using PECVD to form a SiN film. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to further modify Nishimori with the teachings of Harada in order to ensure that excessive out diffusion does not occur
See below for full claims mapping on remaining claims.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-10 are rejected under 35 U.S.C. 103 as being unpatentable over Nishimori (US20160343843A1) in view of Harada (US5350709A).
Regarding claim 1, Nishimori (US20160343843A1) teaches a method for manufacturing a semiconductor device comprising:
ion-implanting impurities into a source-drain electrodes forming region where a source electrode and a drain electrode are to be formed on a nitride semiconductor layer formed on a substrate (Par. 42 “ion implantation is applied with an impurity element such as Si to regions 920 b where n-type regions 920 a are to be formed in the electron supply layer 922 and the electron transit layer 921 immediately below regions where a source electrode 942 and a drain electrode 943 are to be formed”);
forming a silicon nitride film on the surface of the nitride semiconductor layer, the silicon nitride film constituting a surface protecting sacrifice film and a thickness of 100 nm or more and 500 nm or less (Par. 43 “as illustrated in FIG. 2C, a heat-protective film 931 is formed of SiN with the thickness of about 200 nm on the electron supply layer 922”);
heat-treating the nitride semiconductor layer on which the surface protecting sacrifice film is formed (Par. 44 “as illustrated in FIG. 3A, Si-activation annealing is performed. Specifically, RTA (Rapid Thermal Annealing) is performed”); and
removing the surface protecting sacrifice film (Par. 45 “as illustrated in FIG. 3B, the heat-protective film 931 is removed by using a solvent that includes hydrofluoric acid”).
Nishimori does not appear to teach
forming a silicon nitride film on the surface of the nitride semiconductor layer by a plasma-enhanced chemical vapor deposition method; and
the silicon nitride film having a refractive index of 1.80 or more and less than 1.88.
Harada teaches
forming a silicon nitride film on the surface of the nitride semiconductor layer by a plasma-enhanced chemical vapor deposition method (Col. 8 lines 60-63 “[t]he SiOx/SiN composite film is formed using a conventional plasma-enhanced chemical vapor deposition (P-CVD) process”); and
the silicon nitride film having a refractive index of 1.80 or more and less than 1.88 (Col. 10 lines 3-15 “if the refractive index of the SiN film formed by plasma CVD is greater than 1.9” then “the ability to prevent the external diffusion of As” decreases. Therefore, as refractive index of a PECVD deposited layer affects its ability to prevent external diffusion, it is a result effective variable that may be optimized by a person of ordinary skill, see MPEP 2144.05(II)(B). Examiner additionally notes that Harada explicitly teaches “deposition conditions for the SiN film [such that]…the refractive index was 1.8”).
Being in analogous arts, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Nishimori with the teachings of Harada because as both Nishimori and Harada teach a suitable method for forming a SiN film, it would have been obvious to substitute Nishimori’s CVD deposition with Harada’s PECVD deposition to achieve the predictable result of using PECVD to form a SiN film. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to further modify Nishimori with the teachings of Harada in order to ensure that excessive out diffusion does not occur.
Regarding claim 2, Nishimori teaches a method for manufacturing a semiconductor device comprising:
ion-implanting impurities into a source-drain electrodes forming region where a source electrode and a drain electrode are to be formed on a nitride semiconductor layer formed on a substrate (Par. 42 “ion implantation is applied with an impurity element such as Si to regions 920 b where n-type regions 920 a are to be formed in the electron supply layer 922 and the electron transit layer 921 immediately below regions where a source electrode 942 and a drain electrode 943 are to be formed”);
forming a silicon nitride film on the surface of the nitride semiconductor layer, the silicon nitride film constituting a lower surface protecting sacrifice film which is one layer of a surface protecting sacrifice film including two layers of an upper surface protecting sacrifice film and the lower surface protecting sacrifice film (While Nishimori does not explicitly disclose their heat-protective film comprising a plurality of layers, the primary function of the heat-protective film is to be “a protective film when Si-activation annealing is performed later” [Nishimori par. 43]. A duplication of a heat-protective film to form an upper surface protecting sacrifice film would not provide any new or unexpected results as the primary function of being a protective film when Si-activation annealing is performed later is maintained. Additionally, as nothing within the disclosure indicates the presence of new or unexpected results, it would have been obvious to one ordinary skill in the art at the time the claims were effectively filed to therefore duplicate the heat protective film to form an upper surface protecting sacrifice film, see MPEP 2144.04(VI)(B)), the lower surface protecting sacrifice film having a thickness of 30 nm or more (Par. 43 “as illustrated in FIG. 2C, a heat-protective film 931 is formed of SiN with the thickness of about 200 nm on the electron supply layer 922” which examiner notes is greater than 30 nm);
forming the upper surface protecting sacrifice film stacked on the lower surface protecting sacrifice film and having a total thickness of 100 nm or more and 500 nm or less with the lower surface protecting sacrifice film (See above duplication of parts. Par. 43 teaches that “a heat-protective film 931 is formed of SiN with the thickness of about 200 nm on the electron supply layer 922” and so a duplication would result in a bilayer of at least 400 nm which lies in the claimed range);
heat-treating the nitride semiconductor layer on which the surface protecting sacrifice film is formed (Par. 44 “as illustrated in FIG. 3A, Si-activation annealing is performed. Specifically, RTA (Rapid Thermal Annealing) is performed”); and
removing the surface protecting sacrifice film (Par. 45 “as illustrated in FIG. 3B, the heat-protective film 931 is removed by using a solvent that includes hydrofluoric acid”).
Nishimori does not appear to teach
forming a silicon nitride film on the surface of the nitride semiconductor layer by a plasma- enhanced chemical vapor deposition method
the lower surface protecting sacrifice film having a refractive index of 1.80 or more and less than 1.88
Harada teaches
forming a silicon nitride film on the surface of the nitride semiconductor layer by a plasma-enhanced chemical vapor deposition method (Col. 8 lines 60-63 “[t]he SiOx/SiN composite film is formed using a conventional plasma-enhanced chemical vapor deposition (P-CVD) process”); and
the lower surface protecting sacrifice film having a refractive index of 1.80 or more and less than 1.88 (Col. 10 lines 3-15 “if the refractive index of the SiN film formed by plasma CVD is greater than 1.9” then “the ability to prevent the external diffusion of As” decreases. Therefore, as refractive index of a PECVD deposited layer affects its ability to prevent external diffusion, it is a result effective variable that may be optimized by a person of ordinary skill, see MPEP 2144.05(II)(B). Examiner additionally notes that Harada explicitly teaches “deposition conditions for the SiN film [such that]…the refractive index was 1.8”).
Being in analogous arts, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Nishimori with the teachings of Harada because as both Nishimori and Harada teach a suitable method for forming a SiN film, it would have been obvious to substitute Nishimori’s CVD deposition with Harada’s PECVD deposition to achieve the predictable result of using PECVD to form a SiN film. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to further modify Nishimori with the teachings of Harada in order to ensure that excessive out diffusion does not occur.
Regarding claim 3, the combination of Nishimori and Harada teaches the method for manufacturing a semiconductor device according to claim 1, wherein
a heat treatment temperature during heat treatment is 1000 °C or more and 1200 °C or less (Nishimori par. 44 teaches that “RTA (Rapid Thermal Annealing) is performed to heat it for one minute at a temperature about 1100° C” which lies in the claimed range).
Regarding claim 4, the combination of Nishimori and Harada teaches the method for manufacturing a semiconductor device according to claim 1
wherein the source electrode and the drain electrode are made of an electrode material excluding aluminum (Harada col. 18 teaches “an Au/Ni/Au+Ge film which forms ohmic electrodes is deposited by vacuum evaporation” which excludes aluminum. As Nishimori is silent as to the specific composition of their source/drain electrodes, this would motivate a person of ordinary skill in the art to seek out references such as Harada who do explicitly teach materials for use as source/drain electrodes).
Regarding claim 5, the combination of Nishimori and Harada teaches the method for manufacturing a semiconductor device according to claim 1,
wherein the electrode material is any one of titanium, niobium, platinum, and gold, or a combination of two or more thereof (Harada col. 18 teaches “an Au/Ni/Au+Ge film which forms ohmic electrodes is deposited by vacuum evaporation” which comprises gold. As Nishimori is silent as to the specific composition of their source/drain electrodes, this would motivate a person of ordinary skill in the art to seek out references such as Harada who do explicitly teach materials for use as source/drain electrodes).
Regarding claim 6, the combination of Nishimori and Harada teaches the method for manufacturing a semiconductor device according to claim 1,
wherein the surface protecting sacrifice film is removed by wet etching (Nishimori par. 45 teaches “the heat-protective film 931 is removed by using a solvent that includes hydrofluoric acid” which constitutes a wet etching).
Regarding claim 7, the combination of Nishimori and Harada teaches the method for manufacturing a semiconductor device according to claim 2,
wherein a heat treatment temperature during heat treatment is 1000 °C or more and 1200 °C or less (Nishimori par. 44 teaches that “RTA (Rapid Thermal Annealing) is performed to heat it for one minute at a temperature about 1100° C” which lies in the claimed range).
Regarding claim 8, the combination of Nishimori and Harada teaches the method for manufacturing a semiconductor device according to claim 2,
wherein the source electrode and the drain electrode are made of an electrode material excluding aluminum (Harada col. 18 teaches “an Au/Ni/Au+Ge film which forms ohmic electrodes is deposited by vacuum evaporation” which excludes aluminum. As Nishimori is silent as to the specific composition of their source/drain electrodes, this would motivate a person of ordinary skill in the art to seek out references such as Harada who do explicitly teach materials for use as source/drain electrodes).
Regarding claim 9, the combination of Nishimori and Harada teaches the method for manufacturing a semiconductor device according to claim 2,
wherein the electrode material is any one of titanium, niobium, platinum, and gold, or a combination of two or more thereof (Harada col. 18 teaches “an Au/Ni/Au+Ge film which forms ohmic electrodes is deposited by vacuum evaporation” which comprises gold. As Nishimori is silent as to the specific composition of their source/drain electrodes, this would motivate a person of ordinary skill in the art to seek out references such as Harada who do explicitly teach materials for use as source/drain electrodes).
Regarding claim 10, the combination of Nishimori and Harada teaches the method for manufacturing a semiconductor device according to claim 2,
wherein the surface protecting sacrifice film is removed by wet etching (Nishimori par. 45 teaches “the heat-protective film 931 is removed by using a solvent that includes hydrofluoric acid” which constitutes a wet etching).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to COLE LEON LINDSEY whose telephone number is (571)272-4028. The examiner can normally be reached Monday - Friday, 8:00 a.m. - 5:00 p.m..
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Christine Kim can be reached at (571)272-8458. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/COLE LEON LINDSEY/Examiner, Art Unit 2812 /CHRISTINE S. KIM/Supervisory Patent Examiner, Art Unit 2812
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