Prosecution Insights
Last updated: April 19, 2026
Application No. 18/547,107

METHOD FOR MANUFACTURING CIRCUIT SUBSTRATE, AND ELECTRONIC DEVICE

Final Rejection §102
Filed
Aug 18, 2023
Examiner
WILLIS, TREMESHA S
Art Unit
2847
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Hitachi Astemo, Ltd.
OA Round
2 (Final)
78%
Grant Probability
Favorable
3-4
OA Rounds
2y 6m
To Grant
95%
With Interview

Examiner Intelligence

Grants 78% — above average
78%
Career Allow Rate
679 granted / 873 resolved
+9.8% vs TC avg
Strong +18% interview lift
Without
With
+17.5%
Interview Lift
resolved cases with interview
Typical timeline
2y 6m
Avg Prosecution
44 currently pending
Career history
917
Total Applications
across all art units

Statute-Specific Performance

§101
0.2%
-39.8% vs TC avg
§103
31.6%
-8.4% vs TC avg
§102
49.7%
+9.7% vs TC avg
§112
16.8%
-23.2% vs TC avg
Black line = Tech Center average estimate • Based on career data from 873 resolved cases

Office Action

§102
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Response to Amendment Applicant's arguments with respect to claims 1 – 7 have been considered but are moot in view of the new ground(s) of rejection. Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claims 1 – 7 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Nakao et al. (WO 2012/176246). Regarding claim 1, in Figure 6, Nakao discloses a manufacturing method of a circuit board including an annular land portion (2nd land 14) around a through hole (2nd through-hole 12) through which a terminal (2nd lead portion 20) that is an object of a soldering penetrates, and that is soldered on the land portion by a soldering process with a solder supply (40), the manufacturing method comprising: previously forming a preliminary solder (42, 44; solder 42 and solder fillet 44 formed in and on the 1st through-hole 12 are formed before the solder 42 and solder fillet 44 are formed in and on the 2nd through-hole 12) at a position (solder fillet 44 of the 1st through-hole is formed on the left side of the 2nd through-hole 12) opposite to a supply position of the solder (supply unit 40 is on the right side of the 2nd through-hole 12; Figure 6) in the land portion, the position and the supply position being on opposite sides of the through hole before the soldering process (Figure 6). Regarding claim 2, Nakao discloses wherein the land portion is formed into an ellipse shape; and the preliminary solder is formed in a region which is on the side opposite to the supply position of the solder with respect to the through hole, and which includes a first end portion in a major axis direction of the ellipse shape (Figure 6). Regarding claim 3, Nakao discloses wherein the preliminary solder is formed in a second region including a second end portion in the major axis direction of the ellipse shape (Figure 6). Regarding claim 4, Nakao discloses wherein the preliminary solder is formed to include a portion farthest from the supply position of the solder in the land portion (Figure 6). Regarding claim 5, Nakao discloses wherein the circuit board includes a plurality of annular land portions of a first land portion having a relatively large area, and a second land portion having a relatively small area; in the first land portion, the preliminary solder is previously formed at the position opposite to the supply position of the solder with respect to the through hole; and in the second land portion, the preliminary solder is previously formed at a position on a supply position side of the solder with respect to the through hole (Figure 6). Regarding claim 6, Nakao discloses wherein the soldering process is a laser soldering (Figure 6). Regarding claim 7, Nakao discloses wherein the solder is printed and formed on a portion which is an object of a reflow soldering, and a forming region of the preliminary solder in the circuit board; an electronic component is mounted on the portion which is the object of the reflow soldering; and the soldering process is performed to the terminal disposed in the through hole (Figure 6). Conclusion Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to TREMESHA W BURNS whose telephone number is (571)270-3391. The examiner can normally be reached Monday-Friday 8am - 4:30 pm EST. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Timothy Thompson can be reached at (571) 272-2342. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. TREMESHA W. BURNS Primary Examiner Art Unit 2847 /TREMESHA W BURNS/Primary Examiner, Art Unit 2847
Read full office action

Prosecution Timeline

Aug 18, 2023
Application Filed
Sep 06, 2025
Non-Final Rejection — §102
Dec 04, 2025
Examiner Interview Summary
Dec 04, 2025
Applicant Interview (Telephonic)
Dec 10, 2025
Response Filed
Mar 13, 2026
Final Rejection — §102 (current)

Precedent Cases

Applications granted by this same examiner with similar technology

Patent 12604417
COPPER CLAD LAMINATE AND METHOD FOR PRODUCING THE SAME
2y 5m to grant Granted Apr 14, 2026
Patent 12604446
INTEGRATED DEVICE PACKAGE WITH REDUCED THICKNESS
2y 5m to grant Granted Apr 14, 2026
Patent 12604410
ELECTRONIC COMPONENT
2y 5m to grant Granted Apr 14, 2026
Patent 12598702
PRINTED CIRCUIT BOARD
2y 5m to grant Granted Apr 07, 2026
Patent 12598826
IMAGE SENSOR ASSEMBLY
2y 5m to grant Granted Apr 07, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

3-4
Expected OA Rounds
78%
Grant Probability
95%
With Interview (+17.5%)
2y 6m
Median Time to Grant
Moderate
PTA Risk
Based on 873 resolved cases by this examiner. Grant probability derived from career allow rate.

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