DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Preliminary Amendment
Acknowledgement of preliminary amendment dated 08/21/2023 deleting the multiple dependencies from claims 5, 10 and 14 to singular dependent claims.
Domestic Benefit
Present application 18/547,316 filed 08/21/2023 is a National Stage entry of PCT/CN2023/083452 with international filing date of 03/23/2023.
Foreign Priority
Acknowledgment is made of a claim for foreign priority under 35 U.S.C. § 119(a)-(d) or (f). Copies of the certified copies of the priority documents (i.e., application number 202211193866.X filed in China on 09/28/2022) have been received as of 08/21/2023 in this National Stage application from the International Bureau (PCT Rule 17.2(a)).
Information Disclosure Statement
The information disclosure statement submitted on 08/23/2023 was filed before first Office action. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement has been considered.
Specification
The abstract of the disclosure is objected to because last line of abstract states, “latter structure” instead of “ladder structure.” A corrected abstract of the disclosure is required and must be presented on a separate sheet, apart from any other text. See MPEP § 608.01(b).
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The following title OR similar is suggested:
-- SEMICONDUCTOR MEMORY STRUCTURE WITH SUPPORT FRAME IN STAIRCASE REGION AND METHOD OF MAKING THE SAME --.
Claim Objections
Claim 15 is objected to because of the following minor typographical informality: “(114” is missing a right parenthesis. Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-14 and 17-20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1 is indefinite by reciting, “one of the plurality of step” instead of “one of the plurality of steps.” This is grammatically incorrect. "Plurality" must be followed by a plural noun. Further, this recitation implies not that there are multiple steps -- but that there are multiple plurality of steps.
Dependent claims 2-14 do not alleviate the indefiniteness of claim 1 and are rejected for incorporating the indefiniteness from the independent claim.
Claim 2 is indefinite by reciting, “plurality of conductive column” instead of “plurality of conductive columns” This is grammatically incorrect. "Plurality" must be followed by a plural noun. Further, this recitation implies not that there are multiple conductive columns -- but that there are multiple plurality of conductive columns.
Claim 5 is indefinite by reciting, “claims 1” instead of “claim 1.”
Dependent claims 6-9 do not alleviate the indefiniteness of claim 5 and are rejected for incorporating the indefiniteness from the claim.
Claim 17 does not appear to be an “original claim” because the last line of the claim is worded differently and incomplete. Please clarify. It is entirely unclear what the last line means.
Dependent claims 18-20 do not alleviate the indefiniteness of claim 17 and are rejected for incorporating the indefiniteness from the claim 17.
Prior art rejections based on primary reference of Lee.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-3, 10-11 and 15 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by US 2019/0252386 A1 to Lee et al (“Lee”).
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Regarding independent claim 1, Lee teaches of a semiconductor structure (see title: “SEMICONDUCTOR MEMORY DEVICES”), comprising:
a substrate 100 (“substrate”; Figures 5, 6A-6B and for clarity Figure 2; paragraph 0074), wherein the substrate 100 comprises an array region CAR (“cell region”; Figure 2; paragraph 0075) located adjacently, and a peripheral region CTR (“contact region”; Figure 2; paragraph 0074);
a bit line CL1/BL (“first conductive lines” / “bit line”; Figure 6A; paragraphs 0075,0080) extending along a first direction D1, a semiconductor channel CH (“channel region”; best illustrated in Figure 2; paragraph 0042: Figure 2 depicts channel CH extending in direction D2) extending along a second direction D2 and a word line CL2/WL (“second conductive lines” / “word line”; Figure 6B; paragraphs 0075,0089: Figure 6B depicts WL extending in D3 direction) extending along a third direction D3, wherein the bit line CL1/BL, the semiconductor channel CH and the word line CL2/BL are all located in the array region CAR, wherein two of the first direction D1, the second direction D2 and the third direction D3 intersect each other (i.e., as per the coordinate system);
a ladder structure CL1/BL (i.e., see Figure 6A; CTR region has a staircase type stack of CL1/BL alternating with interlayer insulating layers IL) located in the peripheral region CTR, wherein the ladder structure CL1/BL/IL comprises a plurality of steps (see Figure 6A and Examiner’s Annotated Figure 6A supra), wherein each of the plurality of steps (see Figure 6A) is contact-connected to one of the bit line BL (i.e., CL1 in the CTR region is an extension of the BL therefore CL1 is connected to the BL) and the word line (103);
a plurality of conductive columns CNT (“contacts”; Figure 6A; paragraph 0080), wherein each of the plurality of conductive columns CNT is connected to a top surface (see Figure 6A) of one of the plurality of step CL1/BL, wherein an extending direction D3 of the plurality of conductive columns CNT is a same as the extending direction D3 of another of the bit line and the word line CL2/WL (i.e., CNT extends in D3 direction that is same as extending direction of CL2/WL); and
a support frame ILD2 (“interlayered insulation layer”; Figure 6A; paragraph 0080), wherein the support frame ILD2 is located between two adjacent ones (i.e., ILD2 is between adjacent CNTs) of the plurality of conductive columns CNT, and wherein the support frame ILD2 is in contact with each of the plurality of steps (i.e., see Figure 6A: ILD2 directly touches CL1/BL at least at the endpoint in the CTR region);
wherein, along the extending direction D3 of the plurality of conductive columns CNT, a height of the top surface of one of the plurality of steps CL1/BL/IL is different (i.e., hence the step structure of CTR in Figure 6A) from a top surface of another one of the plurality of steps CL1/BL/IL, and wherein two adjacent ones of the plurality of steps CL1/BL/IL are electrically insulated (i.e., through the use of IL and ILD2 of Figure 6A).
Regarding claim 2, Lee teaches in Figure 6A further comprising, along the extension direction D3 of the plurality of conductive column CNT, a first top surface ILD2 touching ILD3, which is a top surface of the support frame ILD2 away from the substrate 100, a second top surface (i.e., top IL closest to ILD3), which is a top surface of a step in the plurality of steps CL1/BL/IL farthest from the substrate 100, wherein the first top surface (i.e., ILD2 closest to ILD3) is not lower (i.e., higher) than the second top surface (i.e., IL closest to ILD3), wherein a bottom surface of the support frame ILD2 close to the substrate 100 is a first bottom surface, and a bottom surface of one of the plurality of steps CL1/BL closest to the substrate 100 is a second bottom surface, and wherein the first bottom surface ILD2 is not higher (i.e., coplanar) than the second bottom surface CL1/BL.
Regarding claim 3, Lee teaches in Figure 2 wherein the plurality of steps CL1/BL is arranged in an array in a plane of the first direction D1 and the second direction D2.
Regarding claim 10, Lee teaches in Figure 2 with Figure 6A wherein the support frame ILD2 is a grid-like structure (i.e., ILD2 surrounds the entirety as illustrated in Figure 6A with spaces for the steps thereby making it grid-like), wherein the grid-like structure comprises a plurality of spaces, wherein the plurality of steps CL1/BL is located in the plurality of spaces corresponding to the plurality of spaces in an one by one correspondence.
Regarding claim 11, Lee teaches wherein a material of the support frame ILD2 comprises at least one of silicon nitride or silicon oxynitride (see paragraph 0064: “…ILD2 may be formed of or include, for example, at least one of silicon oxide, silicon nitride, or silicon oxynitride”).
It is noted that independent method claim 15 is the formation/forming of the structure of independent claim 1, therefore item-to-item matching is performed for claim 15 but explanation may be found in independent claim 1’s rejection supra.
Regarding independent claim 15, Lee teaches in Figures 2, 5 and 6A-6B of a method (see paragraph 0031: “It should be noted that these figures are intended to illustrate the general characteristics of methods and structures”) of fabricating a semiconductor structure (see title: “SEMICONDUCTOR MEMORY DEVICES”), comprising:
providing a substrate 100 having an adjacent array region CAR and a peripheral region CTR;
forming bit lines CL1/BL in the array region CAR extending along a first direction D1, semiconductor channels CH extending along a second direction D2, and word lines CL2/WL extending along a third direction D3, wherein two of the first direction D1, the second direction D2 and the third direction D3 intersect each other; and
forming a ladder structure CL1/BL/IL, conductive columns CNT and a support frame ILD2 in the peripheral region CTR, wherein the ladder structure CL1/BL/IL comprises a plurality of steps CL1/BL/IL, wherein the plurality of steps CL1/BL/IL is in one-to-one contact connection with one of the bit lines (i.e., CL1 is an extension of BL in the CAR region that extends into the CTR region) and the word line CL2/WL; wherein each of the conductive columns CNT is in one-to-one contact connection (see Figure 6A: each CL1 contacts a CNT in the step-like fashion) with each of the plurality of steps CL1/BL/IL, and wherein the conductive column CNT extends in a same direction D3 as another one of the bit lines CL1/BL and the word line CL2/WL (i.e., CNT extends in D3 same as WL);
wherein the support frame ILD2 is located on any adjacent two conductive columns CNT, and is in contact (i.e., ILD2 directly contacts the end portion of CL1/BL) with each of the plurality of steps CL1/BL/IL;
wherein along the extension direction D3 of the conductive columns CNT, a height of a top surface of one of the plurality of steps CL1/BL/IL is different (i.e., hence the step structure of CTR in Figure 6A, refer to Examiner’s Annotated Figure 6A supra) from a height of a top surface of another one of the plurality of steps CL1/BL/IL, and wherein adjacent ones of the plurality of steps CL1/BL/IL are electrically insulated from each other (i.e., through the use of IL and ILD2 of Figure 6A).
Prior art rejections based on primary reference of Yang.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1, 2-3, 11 and 15 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by US 2025/0071976 A1 to Yang et al (“Yang”).
The applied reference has a common Applicant with the instant application1. Based upon the earlier effectively filed date of the reference (i.e., foreign application priority date of 01/03/2023), it constitutes prior art under 35 U.S.C. 102(a)(2) because the foreign application priority date of 01/03/2023 is between the international filing date of present application (i.e., 03/23/2023) and foreign priority date of present application (i.e., 09/28/2022). This rejection under 35 U.S.C. 102(a)(2) might be overcome by: (1) a showing under 37 CFR 1.130(a) that the subject matter disclosed in the reference was obtained directly or indirectly from the inventor or a joint inventor of this application and is thus not prior art in accordance with 35 U.S.C. 102(b)(2)(A); (2) a showing under 37 CFR 1.130(b) of a prior public disclosure under 35 U.S.C. 102(b)(2)(B) if the same invention is not being claimed; (3) a statement pursuant to 35 U.S.C. 102(b)(2)(C) establishing that, not later than the effective filing date of the claimed invention, the subject matter disclosed in the reference and the claimed invention were either owned by the same person or subject to an obligation of assignment to the same person or subject to a joint research agreement; or (4) perfecting foreign priority by providing a certified English translation of the foreign priority document (i.e., 202211193866.X).
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Since the Yang reference appears to have same Applicant as present application, item-to-item matching is shown below with minimal explanation.
Regarding independent claim 1, Yang teaches in Figures 1-2 and 4 of a semiconductor structure (title), comprising:
a substrate 20, wherein the substrate 20 comprises an array region (i.e., memory cell region) located adjacently, and a peripheral region (i.e., stairs 11 that is a contact connection region);
a bit line 10 (see paragraph 0018; Figures 1-2) extending along a first direction D2, a semiconductor channel 12 extending along a second direction D3 and a word line 13 extending along a third direction D1, wherein the bit line 10, the semiconductor channel 12 and the word line 13 are all located in the array region (i.e., memory cell region), wherein two of the first direction D2, the second direction D3 and the third direction D1 intersect each other;
a ladder structure 11 (see paragraph 0019) located in the peripheral region (i.e., contact connection region), wherein the ladder structure 11 comprises a plurality of steps 11 (see Figures 1-2), wherein each of the plurality of steps 11 is contact-connected to one of the bit line 10 (see paragraph 0019: 11 protrudes from 10) and the word line 13;
a plurality of conductive columns 24, wherein each of the plurality of conductive columns 24 is connected to a top surface of one of the plurality of step 11, wherein an extending direction D1 of the plurality of conductive columns 24 is a same as the extending direction D1 of another of the bit line 10 and the word line 13 (i.e., 13 extends in D1 direction); and
a support frame 23, wherein the support frame 23 is located between (see Figure 2) two adjacent ones of the plurality of conductive columns 24, and wherein the support frame 23 is in contact (see Figure 2) with each of the plurality of steps 11;
wherein, along the extending direction D1 of the plurality of conductive columns 23, a height of the top surface of one of the plurality of steps 11 is different (hence the steps of a staircase) from a top surface of another one of the plurality of steps 11, and wherein two adjacent ones of the plurality of steps 11 are electrically insulated (via 23).
Regarding claim 2, Yang teaches further comprising, along the extension direction D1 of the plurality of conductive column 24, a first top surface, which is a top surface of the support frame 23 away from the substrate 30, a second top surface, which is a top surface of a step in the plurality of steps 11 farthest from the substrate 20, wherein the first top surface 23 is not lower than (see Figure 2, higher) the second top surface 11, wherein a bottom surface of the support frame 23 close to the substrate 20 is a first bottom surface, and a bottom surface of one of the plurality of steps 11 closest to the substrate 20 is a second bottom surface, and wherein the first bottom surface 23 is not higher than (i.e., coplanar) the second bottom surface 11.
Regarding claim 3, Yang teaches wherein the plurality of steps 11 is arranged in an array in a plane of the first direction D2 and the second direction D3.
Regarding claim 11, Yang teaches wherein a material of the support frame 23 comprises at least one of silicon nitride (see paragraph 0036) or silicon oxynitride.
Regarding independent method claim 15 that is the forming of the structure of independent structure claim 1; for the sake of compact prosecution the item-to-item matching is not repeated herein. Refer to claim 1 rejections with respect to Yang supra.
Allowable Subject Matter
Claims 4-9 and 12-15 would be allowable if rewritten to overcome the rejections under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph, set forth in this Office action and to include all of the limitations of the base claim and any intervening claims.
Claim 4 contains allowable subject matter, because the closest prior art of record, singularly or in combination, fails to disclose or suggest, in combination with the other elements of claim 4, wherein, along the direction in which the array region (110) points to the peripheral region (120), top surface heights of ones of the plurality of steps (114) arranged at intervals along the first direction (X) gradually decrease, and top surface heights of ones of the plurality of steps (114) arranged at intervals along the second direction (Y) also gradually decrease.
Claim 5 contains allowable subject matter, because the closest prior art of record, singularly or in combination, fails to disclose or suggest, in combination with the other elements of claim 5, wherein the support frame (106) comprises support layers (116), wherein each of the support layers (116) and at least two of the plurality of steps (114) are in contact connection, and wherein the plurality of steps (114) is respectively located on opposite sides of each of the support layers (116) along the first direction (X) and/or on opposite sides of each of the support layers (116) in the second direction (Y).
Dependent claims 6-9 contain allowable subject matter, because they depend on the allowable subject matter of claim 5.
Claim 12 contains allowable subject matter, because the closest prior art of record, singularly or in combination, fails to disclose or suggest, in combination with the other elements of claim 12, wherein the peripheral region (120) comprises a spacer region (130) between the ladder structure (104) and the array region (110), wherein the bit line (101) or the word line (103) is also located in the spacer region (130); and wherein the semiconductor structure further comprises: a peripheral protection layer (107), wherein the peripheral protection layer (107) is located in the spacer region (130) and surrounds a sidewall of the bit line (101) or a sidewall of the word line (103) extending along the first direction (X) in the spacer region (130).
Dependent claims 13-14 contain allowable subject matter, because they depend on the allowable subject matter of claim 12.
Claim 16 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claim 16 contains allowable subject matter, because the closest prior art of record, singularly or in combination, fails to disclose or suggest, in combination with the other elements of claim 16, wherein forming the ladder structure (104) comprises: forming an initial stack structure (108) having multi-layers arranged along the extension direction of the conductive columns (105) in the peripheral region (120), wherein along the extension direction of the conductive columns (105), the initial stack structure (108) comprises a first semiconductor layer (118) and a second semiconductor layer (128) stacked together, wherein the initial stack structure (104) has a pitch region (138) close to the array region (110) and a step region (148) located at on a side of the pitch region (138) away from the array region (110); performing a first patterning process on the initial stacked structure (108) of the step region (148) to form initial ladder structures (124), wherein the initial ladder structures (124) comprise a plurality of initial step structures (134), wherein along the extending direction of the conductive column (105) a height of a top surface of one of the initial step structures (134) is different from a height of a top surface of another initial step structure (134); and etching an initial ladder structure (124) to form spaces in which the plurality of steps (114) are formed.
Claims 17-19 would be allowable if rewritten to overcome the rejections under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph, set forth in this Office action and to include all of the limitations of the base claim and any intervening claims.
Dependent claims 17-20 contain allowable subject, because they depend on the allowable subject matter of claim 16.
Conclusion
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29 November 2025
/John P. Dulka/Primary Examiner, Art Unit 2817
1 Please clarify if present application’s Applicant of ChangXin Memory Technologies, Inc. is the same as the Yang reference’s Applicant of CXMT Corporation.