Prosecution Insights
Last updated: April 19, 2026
Application No. 18/547,344

SEMICONDUCTOR SUBSTRATE, MANUFACTURING METHOD FOR SEMICONDUCTOR SUBSTRATE, AND ELECTRONIC DEVICE HAVING SEMICONDUCTOR SUBSTRATE

Non-Final OA §102§103
Filed
Aug 22, 2023
Examiner
AHMADI, MOHSEN
Art Unit
2896
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Sony Group Corporation
OA Round
1 (Non-Final)
86%
Grant Probability
Favorable
1-2
OA Rounds
2y 6m
To Grant
96%
With Interview

Examiner Intelligence

Grants 86% — above average
86%
Career Allow Rate
384 granted / 446 resolved
+18.1% vs TC avg
Moderate +10% lift
Without
With
+10.0%
Interview Lift
resolved cases with interview
Typical timeline
2y 6m
Avg Prosecution
30 currently pending
Career history
476
Total Applications
across all art units

Statute-Specific Performance

§101
0.2%
-39.8% vs TC avg
§103
49.0%
+9.0% vs TC avg
§102
28.9%
-11.1% vs TC avg
§112
16.4%
-23.6% vs TC avg
Black line = Tech Center average estimate • Based on career data from 446 resolved cases

Office Action

§102 §103
Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . DETAILED ACTION This action is responsive to the application No. 18/547,344 filed on 08/22/2023. Election/Restrictions Applicant’s election without traverse of Species I (claims 1, 3-5, 7 and 8) in the reply filed on 01/06/2026 is acknowledged. Priority Receipt is acknowledged of papers submitted under 35 U.S.C. 119(a)-(d), which papers have been placed of record in the file. Information Disclosure Statement Acknowledgment is made of Applicant’s Information Disclosure Statement (IDS) form PTO-1449. These IDS has been considered. Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claims 1, 3 and 5 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by US Pub # 2003/0137056 to Taniguchi et al. (Taniguchi). Regarding independent claim 1, Taniguchi discloses a semiconductor substrate (Fig. 6) comprising a through electrode (electrode 20 buried in the through hole 40) including: an upper hole portion formed in a forward tapered shape (see Examiner’s markup below); a lower hole portion formed in a reverse tapered shape (see Examiner’s markup below); and a step formed at a boundary between the upper hole portion and the lower hole portion (see Examiner’s markup below) (see also at least ¶0092). PNG media_image1.png 443 794 media_image1.png Greyscale Regarding independent claim 3, Taniguchi discloses a semiconductor substrate (Fig. 6: 16) comprising a through electrode (electrode 20 buried in the through hole 40) including: an upper hole portion formed in a forward tapered shape (see Examiner’s markup below); a lower hole portion formed in a reverse tapered shape (see Examiner’s markup below); and a boundary formed between the upper hole portion and the lower hole portion (see Examiner’s markup below) (see also at least ¶0092). PNG media_image2.png 435 816 media_image2.png Greyscale Regarding claim 5, Taniguchi discloses wherein the through electrode is bored in an interlayer film (Fig.6: 16) having an insulating property (glass 16 is an insulating material). Under the broadest reasonable interpretation, an “interlayer film having an insulating property” encompasses any dielectric/insulating layer or film in which the through electrode opening is formed. Glass is a well-known electrical insulating (dielectric) material, and therefore the glass substrate of Taniguchi inherently possesses the claimed “insulating property.” Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows: 1. Determining the scope and contents of the prior art. 2. Ascertaining the differences between the prior art and the claims at issue. 3. Resolving the level of ordinary skill in the pertinent art. 4. Considering objective evidence present in the application indicating obviousness or nonobviousness. Claims 4 and 7 are rejected under 35 U.S.C. 103 as being unpatentable over US Pub # 2003/0137056 to Taniguchi et al. (Taniguchi). Regarding claim 4, Taniguchi discloses that the through electrode is bored in a glass (Fig. 6: 16) (¶0084). Taniguchi fails to explicitly disclose wherein the through electrode is bored in a silicon. Taniguchi discloses in a different embodiment (Fig. 1: 10 and ¶0028) that the through electrode is bored in a silicon. It would have been obvious to a person having ordinary skill in the art before the effective filing date of the invention to have provided the glass substrate of embodiment of Fig. 6 of Taniguchi to be replaced with the silicon substrate of different embodiment (Fig. 1) of Taniguchi since it has been held that selecting a known material on the basis of its suitability for the intended use involves only routine skill in the art MPEP 2144.07. Additionally, such a modification prevents the generation of leak current (¶0073). Regarding claim 7, Taniguchi discloses wherein the boundary or the step (see Examiner’s markup above from claim1 or 3) between the upper hole portion and the lower hole portion (see Examiner’s markup above from claim1 or 3) is disposed at a position. The written description of Taniguchi does not specifically disclose “a depth direction of 20% to 50% from the opening surface with respect to a depth of the through electrode”. However, although proportions of features in a drawing are not evidence of actual proportions when drawings are not to scale, the description of the article pictured can be relied on, in combination with the drawings, for what they would reasonably teach one of ordinary skill in the art. In re Wright, 569 F.2d 1124, 193 USPQ 332 (CCPA 1977) [MPEP 2125 (II)]. At least Figure (6) of Taniguchi appears to fall within the claimed range or, at the very least, is close to falling within the claimed range. In a case where the claimed ranges overlap or lie inside ranges disclosed by the prior art a prima facie base of obviousness exists. See In re Wertheim, 541 F.2d 257, 191 USPQ 90 (CCPA 1946) [MPEP 2144.05]. Similarly, a prima facie case of obviousness exists where the claimed ranges or amounts do not overlap with the prior art but are merely close. Titanium Metals Corp. of America v. Banner, 778 F.2d 775, 783, 227 USPQ 773, 779 (Fed. Cir. 1985). Furthermore, "[W]here the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation." In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955). After KSR, the presence of a known result-effective variable would be one, but not the only, motivation for a person of ordinary skill in the art to determine the optimum or workable ranges of a variable [MPEP 2144.05(II)(B)]. In the instant case, the only difference between the boundary or the step position of Taniguchi and that of the claims is the claimed range of the depth direction. Because Taniguchi depicts a boundary or step, one skilled in that art would recognize that there are a finite number of identified predictable solutions (i.e. the depth direction must be between 0% and 100%°). As such, absent criticality of the claimed rage, it would have been obvious to one of ordinary skill in the art to pick any the depth direction between 0% and 100%°. Smith v. Nichols, 88 U.S. 112, 118-19 (1874) (a change in form, proportions, or degree "will not sustain a patent"); In re Williams, 36 F.2d 436, 438 (CCPA 1929) ("It is a settled principle of law that a mere carrying forward of an original patented conception involving only change of form, proportions, or degree, or the substitution of equivalents doing the same thing as the original invention, by substantially the same means, is not such an invention as will sustain a patent, even though the changes of the kind may produce better results than prior inventions.") [MPEP 2144.05(II)]. Applicant has NOT demonstrated any criticality to establish that the claimed depth direction of the boundary or step position would perform differently than a prior art device having depth direction of the boundary or step position of the claimed range (see Taniguchi, fig. 6). Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over US Pub # 2003/0137056 to Taniguchi et al. (Taniguchi) in view of US Pub # 2001/0042637 to Hirose et al. (Hirose). Regarding claim 8, Taniguchi discloses a semiconductor substrate structure including a substrate such as glass (Fig. 6) and/or silicon (Fig.5: 36) and a through electrode (Fig. 6: electrode 20 buried in the through hole 40) formed by boring or forming an opening through the substrate and filling the opening with a conductive material (see, e.g., Fig.1: 20). Thus, Taniguchi teaches a through electrode formed in a substrate having an insulating property. However, Taniguchi does not explicitly disclose that the interlayer film having an insulating property is formed by a resin of an organic material or an inorganic material having photosensitivity, as recited in claim 8. Hirose teaches forming interlayer insulating films using a photosensitive resin material (Fig. 3L: 20 and ¶0319) and forming through holes/vias (20a) in the interlayer insulating resin (20) by exposure and development processes (see, e.g., ¶0319 and Figs. 3k-3L). Hirose expressly describes that the interlayer insulating layer is a resin having photosensitivity and provides electrical insulation while permitting photolithographic patterning of openings. It would have been obvious to one of ordinary skill in the art at the time of the invention to form the insulating interlayer film of Taniguchi using the photosensitive resin interlayer insulating film taught by the Hirose publication because the use of photosensitive resin dielectric films for interlayer insulation and via formation was well known and provides the predictable advantages of electrical insulation, process compatibility with photolithography, and facilitated formation of through openings. Substituting or incorporating such a known dielectric resin film into the structure of Taniguchi would have been a routine design choice yielding no more than predictable results. Conclusion The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. US Pat # 6,653170 to Lin, US Pub # 2002/0180015 to Yamaguchi et al., US Pat # 6187418 to Fasano et al., US Pat # 5340947 to Credle et al. Any inquiry concerning this communication or earlier communications from the examiner should be directed to MOHSEN AHMADI whose telephone number is (571)272-5062. The examiner can normally be reached M-F: 9:00am-5:00pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, William F Kraig can be reached at 571-272-8660. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /MOHSEN AHMADI/ Primary Examiner, Art Unit 2896
Read full office action

Prosecution Timeline

Aug 22, 2023
Application Filed
Feb 06, 2026
Non-Final Rejection — §102, §103 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
86%
Grant Probability
96%
With Interview (+10.0%)
2y 6m
Median Time to Grant
Low
PTA Risk
Based on 446 resolved cases by this examiner. Grant probability derived from career allow rate.

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