DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 40,41,43,44 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kamiyasu (JP 2008177496 A).
Regarding claim 40, Kamiyasu et al discloses A component comprising:
a lead frame(2) (pp. 7 para 2); a semiconductor chip(5) (pp. 7 para 2); and
a housing body(3/13) (para 2, pp. 8), wherein the lead frame (2)has a first subregion (2a)and a second subregion (2b)laterally spaced from the first subregion(2a)(pp.7 para 3), wherein the housing body(3/13) laterally encloses the first subregion (2a)and the second subregion(2b) and thereby mechanically connects the first subregion(2a) to the second subregion(2b), wherein the semiconductor chip (5)is arranged on a mounting surface (8)of the first subregion(2a) and is electrically conductively connected to the subregions (2a/2b)of the lead frame(2)(pp. 8 para 2), wherein the first subregion(2a) has a first local elevation(9a), which vertically projects beyond at least one edge region of the first subregion(2a), and, in top view of the mounting surface (8), at least
partially surrounds the semiconductor chip(5)(pp 8 para 2 & 3), wherein, in the top view of the mounting surface(8), the housing body (13)completely covers the first local elevation(9a) and does not cover the semiconductor chip(5) fig. 1 /fig. 2a, and
wherein the first local elevation(9a) is the only local elevation of the first subregion(2a)
projecting along a vertical direction beyond the mounting surface(8) of the first subregion(2a)( fig. 1/fig. 2a-2c).
Regarding claim 41, Kamiyasu et al discloses wherein the first local elevation (9a)is U-shaped and partially or completely encloses the mounting surface fig. 2a.
Regarding claim 43, Kamiyasu et al discloses wherein the first subregion(2a) is one piece with the first local elevation(9a) fig. 2a/fig. 2b.
Regarding claim 44, Kamiyasu et al discloses wherein the second subregion(2b) has a second local elevation(9b) vertically projecting beyond one edge region(11b) of the second subregion(2b), and wherein the first local elevation(9a) and the second local elevation(9b) have the same geometry in the top view fig. 2a.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 21,22,24,30-33,& 35-38 is/are rejected under 35 U.S.C. 103 as being unpatentable over Watanabe (JP 2011119557 A) in view of Oishi (JP 2016174171 A).
Regarding claim 21, Watanabe et al discloses A component comprising: a lead frame(2)(pp. 5 para 1) ; a semiconductor chip(3); and a housing body(4/14)(pp. 5, para 1), wherein the lead frame (2)has a first subregion(7) and a second subregion (8)laterally spaced from the first subregion(7)(pp 5 para 3), wherein the housing body(4/14) (pp 9-10, para 4), laterally encloses the first subregion (7)and the second subregion (8)and thereby mechanically connects the first subregion(7) to the second subregion(8)(para 4 pp 5-6), wherein the semiconductor chip(3) is arranged on a mounting surface(9) of the first subregion(7) and is electrically conductively connected to the subregions(7,8) of the lead frame (2)(para 1 pp. 7), wherein the first subregion (7)has a first local elevation(elevation of region 7 between the recesses 10 & 18)located under element 14), which vertically projects beyond at least one edge region (bottom of 18)of the first subregion(7), and, in top view of the mounting surface(9), at least partially surrounds the semiconductor chip(3), wherein, in the top view of the mounting surface(9) fig. 2, the housing body (14)completely covers the first local elevation (elevation of region 7 between the recesses 10 & 18 located under element 14)and does not cover the semiconductor chip(3) fig.1, wherein the first subregion(7) has a first local depression(10) adjoining the first local elevation(elevation of region 7 between the recesses 10 & 18 located under element 14) fig. 1, the first local depression(10) being completely filled by a material (4)of the housing body(14) fig 1, wherein the mounting surface (9)directly adjoins the first local depression(10) fig. 1, wherein the semiconductor chip(3) is located in close proximity to the first local depression(10) fig. 1,
However, the primary embodiment of Watanabe et al shown in fig. 1 and fig. 2 fails to teach wherein the first local depression additionally serves as a cavity providing space below the mounting surface for phosphors, scattering particles or reflection particles ; and does not explicitly depict the mounting surface comprises an island within the first local depression. Watanabe et al explicitly discloses, in the same embodiment, that the recess 10 may be formed in the vicinity of the slit 6 (formation region of the groove 6A) when the groove 6a is not formed (pp 7-8 para 3). It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to utilize this optional configuration. Furthermore, configuring the island within the first local depression by providing the recess 10 in the vicinity of the slit 6 was a matter of design choice which a person of ordinary skill in the art would have found obvious to implement, absent persuasive evidence that the particular configuration was significant . In re Dailey, 357 F.2d 669, 149 USPQ 47 (CCPA 1966)
However, Oishi et al discloses recess (14) serves as a cavity providing space below the mounting surface for reflection particles added to light reflective resin 31(para 1-3 pp. 20-21). It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify Watanabe et al with the teachings of Oishi et al to improve the light emission efficiency of the optical semiconductor device.
Regarding claim 22, Watanabe et al discloses wherein, in the top view of
the mounting surface (9), the first local elevation (elevation of region 7 between the recesses 10 & 18)extends along at least two or three side surfaces of the semiconductor chip(3) see fig. 2/fig. 1.
Regarding claim 24, Watanabe et al discloses , wherein the first local
elevation (elevation of region 7 between the recesses 10 & 18)has a front-side surface located at the same vertical height as the mounting surface (9) of the first subregion(7 )fig. 1.
Regarding claim 30, Watanabe et al discloses wherein the first local elevation(elevation of region 7 between the recesses 10 & 18) is U-shaped and partially encloses the mounting surface(9) fig. 2 .
Regarding claim 31, Watanabe et al in view of Oishi et al discloses all the claim limitations of claim 21. However, Oishi et al discloses wherein the at least one
edge region (side edge of 11) of the first subregion(11) is formed in a curved manner at
least in regions fig. 7. It would have been obvious to one of ordinary skill in the art before the effective filing date to modify Watanabe et al with the teachings of Oishi et al since modifying the edge was a matter of design choice which a person of ordinary skill in the art would have found obvious to implement, absent persuasive evidence that the particular configuration was significant . In re Dailey, 357 F.2d 669, 149 USPQ 47 (CCPA 1966)
Regarding claim 32, Watanabe et al discloses wherein the first subregion(7)
is one piece with the first local elevation(elevation of region 7 between the recesses 10 & 18) fig. 1.
Regarding claim 33, Watanabe et al discloses wherein the second subregion (8) has a second local elevation (elevation of region 8 between the recesses 10 & 18)vertically projecting beyond one edge region of the second subregion(8), and wherein the first local elevation(elevation of region 7 between the recesses 10 & 18)and the second local elevation(elevation of region 8 between the recesses 10 & 18) have the same geometry in the top view (Examiner notes that the vertical portion have the same geometry) fig. 2.
Regarding claim 35, Watanabe et al in view of Oishi et al discloses all the claim limitations of claim 21. Watanabe et al further teaches the first subregion (7)and/or the second subregion (8)( fig. 1/fig. 2)but fails to teach further comprising: have/has a solder control structure being an integral part of the lead frame, and wherein the solder control structure is visible from an outside on the side surface.
However, Oishi et al discloses a side surface, having a solder control structure(22) being an integral part of the lead frame(21), and wherein the solder control structure(22) is visible from an outside on the side surface fig. 3c (pp1 para 1). It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify Watanabe et al with the teachings of Oishi et al to increase wettability with solder when mounted to external substrate.
Regarding claim 36, Watanabe et al discloses the method comprising: performing a double-etching of a front side of the first subregion (7)of the lead frame(2) for forming the first local elevation( elevation of region 7 between the recesses 10 & 18) on the front side (pp.14-15 pp 3-4; para 2-3 pp. 15); and forming the housing body(4/14), wherein the housing body completely covers the first local elevation (elevation of region 7 between the recesses 10 & 18) and is anchored to the first local elevation(elevation of region 7 between the recesses 10 & 18) fig. 1(pp. 16, para 2-3 fig. 3a(b))
Regarding claim 37, Watanabe et al discloses A method for producing a plurality of components according to claim 21, the method comprising: providing a plurality of lead frames(2), each comprising a first subregion(7) and a second
subregion(8), wherein the first subregions (7)of neighboring lead frames are mechanically connected to one another via connecting bars(22)(pp. 15 para 1-2); performing double-etching for forming the first local elevation (elevation of region 7 between the recesses 10 & 18) on a front side of the respective first subregions(7), wherein the front side is not etched at positions of the connecting
bars(22) (pp.14-15 pp 3-4; para 2-3 pp. 15); and separating the components after forming the housing body(4/14), wherein the housing body(4/14)
and the connecting bars (22)are severed(pp. 21, para 1).
Regarding claim 38, Watanabe et al discloses wherein the second subregions (8)of adjacent lead frames are mechanically connected to one another via further connecting bars(22), and wherein, in performing the double-etching for forming a second local elevation (elevation of region 8 between the recesses 10 & 18) on a front side of the respective second subregions(pp.14-15 pp 3-4; para 2-3 pp. 15), the front side is not etched at positions of the further connecting bars(22), and wherein, when the components are separated, the further connecting bars(22) are severed(pp. 21, para 1).
Claim(s) 23 is/are rejected under 35 U.S.C. 103 as being unpatentable over Watanabe (JP 2011119557 A) in view of Oishi (JP 2016174171 A) as applied to claim 21 and further in view of Oda (JP 2014195127 A).
Regarding claim 23, Watanabe et al as modified by Oishi et al discloses all the claim limitations of claim 21 but fails to teach wherein, in the top view of the mounting surface, the first local elevation completely encloses the semiconductor chip.
However, Oda et al discloses , in the top view of the mounting surface(16), the first local elevation (11a)completely encloses the semiconductor chip(21) (fig. 1/fig. 2,fig. 7). It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to further modify Watanabe et al & Oishi et al with the teachings of Oda et al. to provide a sufficient mounting and reflective surface for the device.
Claim(s) 34 is/are rejected under 35 U.S.C. 103 as being unpatentable over Watanabe (JP 2011119557 A) in view of Oishi (JP 2016174171 A) as applied to claim 21 and further in view of Oshio (US Pub no. 2002/0185649 A1).
Regarding claim 34, Watanabe et al as modified by Oishi et al discloses all the claim limitations of claim 21 but fails to teach further comprising a protection diode arranged on the second subregion of the lead frame and connected antiparallel with the semiconductor chip.
However, Oshio et al discloses a protection diode(106b) arranged on the second
subregion(101) of the lead frame and connected antiparallel with the semiconductor
chip(106b)[0054-0055]. It would have been obvious to one of ordinary skill in the art
before the effective filing date of the invention to further modify Watanabe et al & Oishi et al with the teachings of Oshio et al to protect the semiconductor chip from static electricity.
Claim(s) 42 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kamiyasu (JP 2008177496 A) in view of Oda (JP 2014195127 A).
Regarding claim 42, Kamiyasu et al discloses all the claim limitations of claim 40 but fails to teach wherein the at least one edge region or a plurality of edge regions of the first subregion is formed in a curved manner at least in regions.
However, Oda et al discloses wherein the at least one edge region (17) of the first subregion(11a) is formed in a curved manner at least in regions(pp. 7 para 1). It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify Kamiyasu et al with the teachings of Oda et al since modifying the edge was a matter of design choice which a person of ordinary skill in the art would have found obvious to implement, absent persuasive evidence that the particular configuration was significant . In re Dailey, 357 F.2d 669, 149 USPQ 47 (CCPA 1966)
Claim(s) 45 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kamiyasu (JP 2008177496 A) in view of Oshio (US Pub no. 2002/0185649 A1).
Regarding claim 45, Kamiyasu et al discloses all the claim limitations of claim 40 but fails to teach further comprising a protection diode arranged on the second subregion of the lead frame and connected antiparallel with the semiconductor chip.
However, Oshio et al discloses a protection diode(106b) arranged on the second
subregion(101) of the lead frame and connected antiparallel with the semiconductor
chip(106b)[0054-0055]. It would have been obvious to one of ordinary skill in the art
before the effective filing date of the invention to further modify Kamiyasu et al with the
teachings of Oshio et al to protect the semiconductor chip from static electricity.
Claim(s) 46 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kamiyasu (JP 2008177496 A) in view of Oishi (JP 2016174171 A).
Regarding claim 46, Kamiyasu et al discloses all the claim limitations of claim 40 and further teaches, the first subregion (2a)and/or the second subregion (2b)( fig. 2a/2b)but fails to teach further comprising: have/has a solder control structure being an integral part of the lead frame, and wherein the solder control structure is visible from an outside on the side surface.
However, Oishi et al discloses a side surface, having a solder control structure(22) being an integral part of the lead frame(21), and wherein the solder control structure(22) is visible from an outside on the side surface fig. 3c (pp1 para 1). It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify Kamiyasu et al with the teachings of Oishi et al to increase wettability with solder when mounted to external substrate.
Response to Arguments
Applicant’s arguments, see remarks, filed 6/29/2026, with respect to the rejection(s) of claim(s) 21 & 40 under 102(a) (1) and 35 U.S.C. 103 have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of Watanabe (JP 2011119557 A) in view of Oishi (JP 2016174171 A) (claim 21) and Kamiyasu (JP 2008177496 A)(claim 40).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to LATANYA N CRAWFORD EASON whose telephone number is (571)270-3208. The examiner can normally be reached Monday-Friday 8:30 AM-4:30 PM.
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/LATANYA N CRAWFORD EASON/Primary Examiner, Art Unit 2813
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