DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 21-24 & 30-36 & 46 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 21 recites the limitation "the depression" in line 18 . There is insufficient antecedent basis for this limitation in the claim.
Claim 46 recites the limitation "the component". There is insufficient antecedent basis for this limitation in the claim.
Claim Rejections - 35 USC § 102/103
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 21, 22, 24-33, 35-38 & 40 is/are rejected under 35 U.S.C. 102(a)(1) as anticipated by or, in the alternative, under 35 U.S.C. 103 as obvious over Oishi (JP 2016174171 A).
Regarding claim 21, Oishi et al discloses A component (fig. 5a/fig. 6a) comprising: a lead frame(10) (pp. 6,para 2); a semiconductor chip(42)(pp. 13, para 3); and a housing body (31)(pp. 14,para 1), wherein the lead frame (10)has a first subregion (11)and a second subregion(12) laterally spaced from the first subregion(11) (pp. 6,para 2), wherein the housing body (31) laterally encloses the first subregion (11) and the second subregion (12)and thereby mechanically connects the first subregion(11) to the second subregion(12) (pp. 21,para 3), wherein the semiconductor chip(42) is arranged on a mounting surface of the first subregion (11)and is electrically conductively connected to the subregions (11/12) of the lead frame(10)(pp.25 , para 2, lines 8-12), wherein the first subregion has a first local elevation (projection created by (14) , which vertically projects beyond at least one edge region of the first subregion(11), and, in top view of the mounting surface, at least partially surrounds the semiconductor chip(42) (fig. 5a/6a), and wherein, in the top view of the mounting surface, the housing body (31)completely covers the first local elevation (outer surface projection created by (14)) and does not cover the semiconductor chip(42) (fig. 5a/6a),
wherein the first subregion(11) has a first local depression (14) adjoining the first local elevation(outer surface projection created by (14)) fig. 5a, the first local depression(14) being completely filled by a material of the housing body(31)(pp. 22, para 3), wherein the mounting surface is formed as an island (the island of the terminal portion 11 demarcated by recess 14)within the depression(14) fig. 7, wherein the mounting surface directly adjoins the first local depression(14) fig. 7 /fig. 8, wherein the semiconductor chip(42) is located in close proximity to the first local depression(14) fig. 8, and wherein the first local depression(14) additionally serves as a cavity providing space below the mounting surface fig. 5a/fig. 7 but fails to teach the limitation of “ for phosphors, scattering particles or reflection particles. Since Oishi et al teaches the same or similar structure(cavity /local depression-14 of fig 5a/fig. 7) as applicants invention(depression 11V fig. 1b) a prima facie case of either anticipation or obviousness exists and the cavity of Oishi et al would necessarily possess the characteristics of serving as a cavity for phosphors, scattering particles or reflection particles . In re Best, 562 F.2d at 1255, 195 USPQ at 433. See also Titanium Metals Corp. v. Banner, 778 F.2d 775, 227 USPQ 773 (Fed. Cir. 1985) The limitation of “for phosphors, scattering particles or reflection particles” is intended use. A claim containing a "recitation with respect to the manner in which a claimed apparatus is intended to be employed does not differentiate the claimed apparatus from a prior art apparatus" if the prior art apparatus teaches all the structural limitations of the claim. Ex parte Masham, 2 USPQ2d 1647 (Bd. Pat. App. & Inter. 1987)
Regarding claim 22, Oishi et al discloses wherein, in the top view of the mounting surface, the first local elevation (outer surface projection created by (14-14a or 14b)) extends along at least two or three side surfaces of the semiconductor chip(42) fig. 6a or fig. 6b /fig. 5a/fig. 5b).
Regarding claim 24, Oishi et al discloses wherein the first local elevation (outer surface projection created by (14-14a or 14b)) has a front-side surface located at the same vertical height as the mounting surface of the first subregion(11) fig. 5a/fig. 7.
Regarding claim 30, Oishi et al discloses wherein the first local elevation(outer surface projection created by (14-14a or 14b)) is U- shaped or frame-shaped and partially or completely encloses the mounting surface fig. 6a/fig. 6b.
Regarding claim 31, Oishi et al discloses wherein at least one edge region or a
plurality of edge regions of the first subregion(11) is formed in a curved manner at least in regions fig. 7.
Regarding claim 32, Oishi et al discloses wherein the first subregion (11) is one piece with the first local elevation(outer surface projection created by (14/14a or 14b)) fig. 6a-6c/fig. 5a,fig. 5b.
Regarding claim 33, Oishi et al discloses wherein the second subregion (12) has a second local elevation(outer surface projection created by (14/14a or 14b)) vertically projecting beyond one edge region of the second subregion(12), and wherein the first local elevation(outer surface projection created by (14/14a or 14b)) and the second local elevation(outer surface projection created by (14/14a or 14b)) have the same geometry in the top view fig. 6a-6c.
Regarding claim 35, Oishi et al discloses wherein the first subregion (11)and/or the second subregion(12) have/has a solder control structure (13a) being an integral part of the lead frame(10 of 2), and wherein the solder control structure (13a)is visible from an outside on a side surface of the component (fig. 2).
Regarding claim 36 Oishi et al discloses A method for producing the component according to claim 21, the method comprising: performing a double-etching of a front side of the first subregion (11) of the lead frame (10)for forming the first local elevation (outer surface projection created by (14-14a and 14b))on the front side; and forming the housing body(31), wherein the housing body(31) completely covers the first local elevation (outer surface projection created by (14-14a and 14b))and is anchored to
the first local elevation(outer surface projection created by (14-14a or 14b)) (pp. 16, para 2 and pp 28 para5 and pp29, para 1).
Regarding claim 37, Oishi et al discloses A method for producing a plurality of components according to claim 21, the method comprising: providing a plurality of lead frames (10 of 2), each comprising a first subregion(11) and a second subregion(12) fig. 2, wherein the first subregions (11)of neighboring lead frames(10 of 2) are mechanically connected to one another via connecting bars(13a/13b)(pp 6 para 3); performing double-etching for forming the first local elevation(outer surface projection created by (14-14a and 14b)) on a front side of the respective first subregions(11), wherein the front side is not etched at positions of the connecting bars(13a/13b); and separating the components after forming the housing body(31), wherein the housing body (31)and the connecting bars (13a,13b)are severed(p. 13, para 1-3).
Regarding claim 38, Oishi et al discloses wherein the second subregions (12) of adjacent lead frames (10 of 2)are mechanically connected to one another via further connecting bars(13a,13b), and wherein, in performing the double-etching for forming a second local elevation (outer surface projection created by (14-14a and 14b)) on a front side of the respective second subregions(12), the front side is not etched at positions of the further connecting bars(13a,13b) )(pp 6 para 3), and wherein, when the components are separated, the further connecting bars are severed(p. 13, para 1-3).
Regarding claim 40, Oishi et al discloses A component comprising: a lead frame(10) (pp. 6,para 2); a semiconductor chip(42) (pp. 13, para 3); and a housing body(31) (pp. 14, para 1), wherein the lead frame (10)has a first subregion(11) and a second subregion (12)laterally spaced from the first subregion(11) (pp. 6,para 2), wherein the housing body(31) laterally encloses the first subregion(11) and the second subregion(12) and thereby mechanically connects the first subregion (11)to the second subregion(12) (pp. 20, para 3), wherein the semiconductor chip (42)is arranged on a mounting surface of the first subregion(11) and is electrically conductively connected to the subregions(12) of the lead frame(10), (pp. 25, para 1 lines 1-2) wherein the first subregion (11)has a first local elevation(outer surface projection created by (14)), which vertically projects beyond at least one edge region of the first subregion(11) fig. 5a/fig. 7-the outer edge of (11) projects vertically in the y direction in plan view), and, in top view of the mounting surface, at least partially surrounds the semiconductor chip(42) fig. 6b, wherein, in the top view of the mounting surface, the housing body (31)completely covers the first local elevation outer surface projection created by (14)) and does not cover the semiconductor chip(42) (fig. 5a/fig. 6b), and wherein the first local elevation (outer surface projection created by (14))is the only local elevation of the first subregion(the outer surface projection created by 14 is one entire outside region (11)on the outside of 14 that projects laterally from the mounting surface outside the recess 14) projecting along a vertical direction beyond the mounting surface of the first subregion(11) fig. 5a/ fig. 7.
Regarding claim 41, Oishi et al discloses wherein the first local elevation is U- shaped or frame-shaped and partially encloses the mounting surface (11 surrounded by 14) .
Regarding claim 42, Oishi et al discloses wherein the at least one edge region or a plurality of edge regions of the first subregion(11) is formed in a curved manner at least in regions(the edges of the recess 14 are curved).
Regarding claim 43, Oishi et al discloses wherein the first subregion(11) is one piece
with the first local elevation(outer portion of 11 outside of 14).
Regarding claim 44, Oishi et al discloses wherein the second subregion(12) has a second local elevation vertically projecting beyond one edge region of the second subregion(12), and wherein the first local elevation (regions outside 14 of 11 & 12)and the second local elevation have the same geometry in the top view fig, 7b.
Regarding claim 46, Oishi et al discloses wherein the first subregion(11) and/or the second subregion(12) have/has a solder control structure(22) being an integral part of the lead frame(21), and wherein the solder control structure(22) is visible from an outside on a side surface of the component fig. 3c (pp 11 para 1).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 23 is/are rejected under 35 U.S.C. 103 as being unpatentable over Oishi (JP 2016174171 A) in view of Oda (JP 2014195127 A).
Regarding claim 23, Oishi et al discloses all the claim limitations of claim 21 but fails to teach wherein, in the top view of the mounting surface, the first local elevation completely encloses the semiconductor chip.
However, Oda et al discloses in the top view of the mounting surface(14), the first local elevation (surface projection created by (17 and 15)) completely encloses the semiconductor chip (21)(abstract)pp. 15 (para 3) & 16(para 1) fig. 7a to 7f. It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify Oishi et al with the teachings of Oda et al to reduce the thickness of the semiconductor device.
Claim(s) 34 is/are rejected under 35 U.S.C. 103 as being unpatentable over Oishi (JP 2016174171 A) in view of Bogner (US Pub no. 2011/0121336 A1).
Regarding claim 34, Oishi et al discloses all the claim limitations of claim 21 but fails to teach comprising a protection diode arranged on the second subregion of the lead frame and connected antiparallel with semiconductor chip.
However, Bogner et al discloses comprising a protection diode(313) arranged on the second subregion (308)of the lead frame and connected antiparallel with semiconductor chip(301)[0056] fig. 3. It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify Oishi et al with the teachings of Bogner et al to provide protection against damage caused by electrostatic charging.
Claim(s) 45 is/are rejected under 35 U.S.C. 103 as being unpatentable over Oishi (JP 2016174171 A) in view of Oshio (US Pub no. 2002/0185649 A1).
Regarding claim 45, Oishi et al discloses all the claim limitations of claim 40 but fails to teach further comprising a protection diode arranged on the second subregion of the lead frame and connected antiparallel with the semiconductor chip.
However, Oshio et al discloses a protection diode(106b) arranged on the second subregion(101) of the lead frame and connected antiparallel with the semiconductor chip(106b)[0054-0055]. It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to further modify Oishi et al with the teachings of Oshio et al to protect the semiconductor chip from static electricity.
Response to Arguments
Applicant's arguments filed 1/ 9/ 2026 have been fully considered but they are not persuasive. Applicant argues that Oishi merely describes, in connection with Figures 6a to 8b, a mounting surface that is enclosed in lateral directions by discontinuous recesses 14, 14a and 14c. This mounting surface does not form an island or is an island-like structure within a recess. Further, Oishi does not describe the semiconductor chip 42 being located in close proximity the local recesses 14a or 14c, with the local recess 14a or 14b additionally serving as a cavity that provides space for phosphors, scattering particles, or reflective particles below the mounting surface.
Oishi neither teaches nor suggests a local elevation of the lead frame, wherein the local elevation not only vertically projects beyond one edge region of the lead frame but also vertically projects beyond a mounting surface of the lead frame.
Examiner notes that Oishi et al discloses a recess 14 and the island structure is represented by terminal portion 11 within the recess 14. The claim does not require that the depression has to be continuous to represent an island.
With regards to the semiconductor chip being in close proximity to the local recesses, Examiner notes that the term “close proximity “ is relative and the semiconductor chip 42 resides on terminal portion 11 near the recess 14 . The recess further serves as a cavity since its being filled with material 31 fig. 7a. The limitation of “for phosphors, scattering particles, or reflective particles below the mounting surface” asserts intended use language and therefore a claim containing a "recitation with respect to the manner in which a claimed apparatus is intended to be employed does not differentiate the claimed apparatus from a prior art apparatus" if the prior art apparatus teaches all the structural limitations of the claim. Ex parte Masham, 2 USPQ2d 1647 (Bd. Pat. App. & Inter. 1987). A recitation of the intended use of the claimed invention must result in a structural difference between the claimed invention and the prior art in order to patentably distinguish the claimed invention from the prior art. If the prior art structure is capable of performing the intended use, then it meets the claim.
Oishi further teaches the limitation of “projecting along a vertical direction beyond the mounting surface of the first subregion”. As shown below, using the arrow to indicate the edge region where the local elevation begins, fig. 7a shows a vertical projection existing outside of recess 14 which extends laterally beyond the mounting region (represented by region 11 inside of 14), therefore the local elevation extends vertically while simultaneously extending laterally beyond the mounting region. Oishi is maintained.
PNG
media_image1.png
237
511
media_image1.png
Greyscale
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to LATANYA N CRAWFORD EASON whose telephone number is (571)270-3208. The examiner can normally be reached Monday-Friday 8:30 AM-4:30 PM.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Steven B Gauthier can be reached at (571)270-0373. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/LATANYA N CRAWFORD EASON/Primary Examiner, Art Unit 2813
Prosecution Insights