DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Park KR20200022626 (Prior art submitted by the applicant on 8/23/2023)
Regarding Claim 1 in paragraphs 0021-0024 and in Figs. 2-5, Park discloses a method of forming side wirings on a circuit panel, which includes a substrate 110, a first circuit 130 formed on a top surface of the substrate, and a plurality of upper electrodes 140 formed on one side of the top surface of the substrate corresponding to the first circuit, the method comprising steps of: providing a second circuit 150 provided at lower portion of the substrate and a plurality of lower electrodes 160 formed on one side of the second circuit; providing a side film 200 and a plurality of conductive patterns 240 formed parallel to each other on the side film; adhering (using element adhesive layer 250) the side film to the one side of the top surface, a side wall, the one side of the bottom surface of the substrate 110 to cover the upper electrodes 140 and the lower electrodes 160; and electrically connecting the upper electrodes and the lower electrodes using the conductive patterns 240; wherein an anisotropic conductive layer (see paragraph 0034, Fig. 2 along with Fig. 7, element 260 (ACF) for “anisotropic conductive layer” limitation) of the side film connect the conductive patterns to at least one of the upper electrodes and the lower electrodes.
Regarding Claim 2, in Fig. 7, the anisotropic conductive layer (ACF) is formed using an anisotropic conductive paste (namely a thermosetting pressure silver paste)
Regarding Claim 3, Figs. 6 and 7, the conductive patterns 240 are formed using a metal thick film (please note the claim language does not define what “thick” is).
Regarding Claim 4, in Figs. 4 and 5, a pair of the upper electrode 140/242/244 and the lower electrode 160/242/244 electrically connected to each other are connected by at least two or more conductive patterns 240, and at least one dummy conductive pattern 240 exists at intervals of adjacent groups of the conductive patterns connecting the upper electrodes and the lower electrodes, and wherein the dummy conductive pattern 240 is not connected to the first circuit 130 and the second circuit 150.
Regarding Claim 5, the second circuit 150 and the lower electrodes 160 are formed on the bottom surface of the substrate 110.
Regarding Claim 6, the second circuit 150 and the lower electrodes 160 are formed on another substrate 110 different from the substrate on which the first circuit 130 and the upper electrodes 140 are formed.
Regarding Claim 7, in Figs. 4, 5, 6 and 7, the conductive patterns 240 are formed on an inner surface of the side film, an extension substrate 110 (the right side portion) is provided with an outer surface on which extension conductive patterns 240 are formed corresponding to the conductive patterns and an inner surface on which an adhesive layer 250 is formed, the conductive patterns of the side film and the extension conductive patterns of the extension substrate are electrically connected with an anisotropic conductive layer (ACF/260), and the extension substrate is adhered to the bottom surface or the side of the circuit panel, allowing the side film 200 and the conductive patterns 240 to adhere to the side of the circuit panel.
Regarding Claim 8, a step of transferring the conductive patterns 240 to the substrate, by separating the side film 200 (please note that element 200 is also called a ‘signal transfer sheet” or “signal transmission sheet”) and remaining the conductive patterns on the side of the substrate 110.
Regarding Claim 9, the two end portions of conductive patterns 240 (where the ends are also labeled as 242/244 in Fig. 4 for example) relatively narrower than the middle portion of conductive patterns (please note that the language relatively makes the prior are Fig. 4 read on the claim)
Regarding Claim 10, in in paragraphs 0021-0024 and in Figs. 2-5, Park discloses a circuit panel having side wirings, comprising: a substrate 110 including a first circuit 130 formed on a top surface of the substrate and a plurality of upper electrodes 140 formed on one side of the top surface of the substrate corresponding to the first circuit; a side film 200 adhered (by adhesive layer 250) to the top surface, a side wall and a bottom surface of the substrate, with a plurality of conductive patterns 240 formed parallel to each other on the side film; and a second circuit 150 including a plurality of lower electrodes 160 connected to the conductive patterns to communicate with the first circuit; wherein ananisotropic conductive layer (“ACF”, see paragraph 0034, Fig. 2 along with Fig. 7, element 260) of the side film 200 connect the conductive patterns 240 to at least one of the upper electrodes 140 and the lower electrodes 160.
Regarding Claim 11, the anisotropic conductive layer (ACF, 260 in Fig. 7) is formed using ananisotropic conductive paste (namely thermosetting pressure silver paste)
Regarding Claim 12, the conductive patterns 240 are formed using a metal thick film. (please note that the claim language does not define what “thick” is)
Regarding Claim 13, a pair of the upper electrode 140/242 and the lower electrode 160/242 electrically connected to each other are connected by at least two or more conductive patterns, and at least one dummy conductive pattern 240 exists at intervals of adjacent groups of the conductive patterns connecting the upper electrodes 140/242 and the lower electrodes 160/242, and wherein the dummy conductive pattern 240 is not connected to the first circuit 130 and the second circuit 150.
Regarding Claim 14, the second circuit 150 and the lower electrodes 160 are formed on the bottom surface of the substrate 110.
Regarding Claim 15, the second circuit 150 and the lower electrodes 160 are formed on another substrate 110 different from the substrate 110 on which the first circuit 130 and the upper electrodes 140 are formed.
Regarding Claim 16, the conductive patterns 240 are formed on an inner surface of the side film 200,an extension substrate (right end portion of element 110) is provided with an outer surface on which extension conductive patterns 240 are formed corresponding to the conductive patterns and an inner surface on which an adhesive layer 250 is formed, the conductive patterns of the side film and the extension conductive patterns of the extension substrate are electrically connected (please note that element 200 is defined as signal transfer/transmission sheet by the prior art) with an anisotropic conductive layer (ACF/260), and the extension substrate is adhered to the bottom surface or the side of the circuit panel, allowing the side film 200 and the conductive patterns 240 to adhere to the side of the circuit panel.
Regarding Claim 17, the two end portions of conductive patterns 240 (which are also labeled as 242/244 in Fig. 4) are relatively narrower than the middle portion of conductive patterns.
Regarding Claim 18, in paragraphs 0021-0024 and in Figs. 2-5, Park discloses an extension adapter added to a circuit panel which includes a substrate 110, a first circuit 130 formed on a top surface of the substrate and a plurality of upper electrodes 140 formed on one side of the top surface of the substrate corresponding to the first circuit, to form side wirings connecting the first circuit and another circuit except the first circuit, the extension adapter comprising: a side film 200/230/240/250 including a plurality of conductive patterns 240 formed parallel to each other on an inner side of the side film; an extension substrate (right end portion of element 110) including extension conductive patterns 240 formed on an outer side of the extension substrate corresponding to the conductive patterns; and an adhesive layer 250 formed on an inner side of the extension substrate; wherein the extension substrate (right end portion of element 110) is adhered to the bottom surface or the side of the circuit panel, allowing the side film and the conductive patterns to adhere to the side of the circuit panel.
Regarding Claim 19, in Figs. 6 and 7, an anisotropic conductive layer (ACF/260) connects the conductive patterns 240 of the side film and the extension conductive patterns 240 of the extension substrate 110.
Regarding Claim 20, in Fig. 6, a release film 220 is provided on the inner side of the adhesive layer.
Examiner is including, in attached PTO 892 form, following pertinent prior art references that are not relied upon on this rejection, but that do disclose (micro-led) array display panel structure with dual/double sided substrate with side connection/wiring between the upper and the lower portions where the micro led devices are located on top/upper of the panel and the driver circuitry is located on the bottom/rear of the display panel.
Lim 20210066432
Zheng 20200142237
Kwon 20220157916
Lu 20220384492
Conclusion
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/FAZLI ERDEM/Primary Examiner, Art Unit 2812 11/14/2025