DETAILED ACTION
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore elements, ‘etching stop structure’ cited in claims 2-3, 8, must be shown or the feature(s) canceled from the claim(s). No new matter should be entered.
claims 2-3, 8:
wherein the etching stop structure is formed to enter a lower layer of the cap layer in a thickness direction.
Referring to fig. 1-5, etching stop structure 113/114 is isolated by the insulating layer 109 from the lower layer (e.g., 121, 105) of the cap layer (106). Thus, there is no access to the bottom layers thru the etching stop structures.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-11 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by TAKAZAWA HIROYUKI et al. (JP 2002368014 A, hereinafter Takazawa‘014).
Regarding independent claim 1, Takazawa‘014 teaches, “A field effect transistor (fig. 1-11; ¶ [0007] - ¶ [0040]) comprising:
a buffer layer (11), a channel layer (14), a barrier layer (17), a carrier supply layer (16), and a cap layer (20) formed on a semiconductor substrate (1);
a source electrode (4) and a drain electrode formed to be separated from each other on the cap layer (20);
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an insulating layer (30) formed on the cap layer (20) between the source electrode (4) and the drain electrode (5) and having an opening (40);
a recess region (50) formed in the cap layer (20) between the source electrode (4) and the drain electrode (5);
a gate electrode (6) disposed between the source electrode (4) and the drain electrode (5), formed on the insulating layer (30), and partially fitted into the recess region (50) through the opening (40); and
an etching stop structure (part of insulating film 30, see annotation) formed on at least one of a first side surface of the recess region that is a boundary between the cap layer on the source electrode side and the recess region and a second side surface of the recess region (50) that is a boundary between the cap layer (20) on the drain electrode side (5) and the recess region (50)”.
Regarding claim 2, Takazawa‘014 further teaches, “The field effect transistor according to claim 1, wherein a gap between the opening (40) and the second side surface (facing drain 5) is larger than a gap between the opening (40) and the first side surface (facing source 4)”.
Regarding claim 3 and 8, Takazawa‘014 further teaches, The field effect transistor according to claim 1/2, “wherein the etching stop structure is formed to enter a lower layer (19) of the cap layer (20) in a thickness direction”.
Regarding claim 4 and 9-10, Takazawa‘014 further teaches, “The field effect transistor according to claim 1/2/3, “further comprising an etching stop layer (19) formed between the carrier supply layer (16) and the cap layer (20)”.
Regarding independent claim 5, Takazawa‘014 teaches, “A method of manufacturing a field effect transistor (fig. 2-6; ¶ [0007] - ¶ [0040]), comprising:
a first step (fig. 2) of forming a buffer layer (11), a channel layer (14), a barrier layer (17), a carrier supply layer (16), and a cap layer (20) on a semiconductor substrate (1);
a second step (fig. 3) of forming a source electrode (4) and a drain electrode (5) to be separated from each other on the cap layer (20);
a third step (fig. 5) of forming a groove (50) extending in a gate width direction in the cap layer (20) at a position corresponding to at least one of a boundary on a side of the source electrode (4) in a region used as a recess region (50) and a boundary on a side of the drain electrode (5) in a region used as a recess region (50);
a fourth step (fig. 5) of forming an etching stop structure (part of insulating film 30) on at least one of a first side surface of the recess region that is a boundary between the cap layer on the source electrode side of the groove and the recess region and a second side surface of the recess region (50) that is a boundary between the cap layer (20) on the drain electrode (5) side of the groove (50) and the recess region (50);
a fifth step (fig. 4) of forming an insulating layer (30) between the source electrode (4) and the drain electrode (5) on the cap layer (20) in which the groove (50) is formed;
a sixth step (fig. 4) of forming an opening (41) in the insulating layer (30);
a seventh step (fig. 5) of forming the recess region (50) in the cap layer (20) below the opening (41) by etching the cap layer (20) from the opening (41) to the etching stop structure (see annotation) in a direction of the source electrode and a direction of the drain electrode in a plan view of a part of the cap layer through an etching process using the insulating layer (30) having the opening as a mask; and
an eighth step (fig. 6) of depositing a gate electrode material on the insulating layer (30) to form a gate electrode (6) that is disposed on the insulating layer (30), is partially fitted into the recess region (50) through the opening (41), and includes a main portion made of the gate electrode material and a plunged portion disposed between the main portion and the barrier layer (17)”.
Regarding claim 6, Takazawa‘014 further teaches, “The method of manufacturing a field effect transistor according to claim 5, wherein the fourth step and the fifth step are performed by forming the insulating layer (30, fig. 4-5) on the cap layer (20) in which the groove (50) is formed to allow the insulating layer (20) to enter the recess region in the groove (50), and forming the etching stop structure (see annotation) on at least one of the first side surface of the recess region (50) that is a boundary between the cap layer (20) on the source electrode (4) side and the recess region (50) and the second side surface of the recess region that is a boundary between the cap layer (20) on the drain electrode side and the recess region”.
Regarding claims 7 and 11, Takazawa‘014 further teaches, The method of manufacturing a field effect transistor according to claim 7/11, “wherein in the first step, the buffer layer (11), the channel layer (14), the barrier layer (17), the carrier supply layer (16), the etching stop layer (19), and the cap layer (20) are formed on the semiconductor substrate (1), and in the seventh step (fig. 5), the recess region (50) is formed by performing etching to the etching stop layer in a thickness direction”.
Examiner’s Note
The prior arts cited in PTO-892 but not used in the current rejection are related to the claimed novelty.
Applicant is reminded that the Examiner is entitled to give the broadest reasonable interpretation to the language of the claims. Furthermore, the Examiner is not limited to Applicants' definition which is not specifically set forth in the claims. See MPEP 2111, 2123, 2125, 2141.02 VI, and 2182.
Examiner has cited particular columns and line numbers in the references applied to the claims above for the convenience of the applicant. Although the specified citations are representative of the teachings of the art and are applied to specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested from the applicant in preparing responses, to fully consider the references in their entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the Examiner. See MPEP 2141.02 VI.
In the case of amending the claimed invention, Applicant is respectfully requested to indicate the portion(s) of the specification which dictate(s) the structure relied on for proper interpretation and also to verify and ascertain the metes and bounds of the claimed invention.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MOHAMMAD M HOQUE whose telephone number is (571)272-6266 and email address is mohammad.hoque@uspto.gov. The examiner can normally be reached 9AM-7PM EST.
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/MOHAMMAD M HOQUE/Primary Examiner, Art Unit 2817