DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Claims 15 - 20 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected Group, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on December 29, 2025.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claims 1, 3, 9, and 11 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. In particular, lines 14 – 15 of claim 1 (and claims 3, 9, and 11 similarly) recite “wherein the circuit assembly causes the at least one gap to heal.” It is not clear as to what is meant by ‘causing the gap to heal’ or ‘how the gap is healed.’
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1 – 14 are rejected under 35 U.S.C. 103 as being unpatentable over Iwase et al. (U.S. Patent Publication No. 2014/0138125).
Regarding claim 1, in Figures 2A – 2D, Iwase discloses a method for manufacturing a circuit assembly, the method comprising: providing a substrate layer (200) comprising a substrate material; placing a removable stencil (10) comprising a stencil material on a surface of the substrate layer, wherein the removable stencil has a thickness and a pattern of passages formed therein (screen printing plate 10 has line patterns 20 formed therethrough, paragraph [0036]; Figures 1A – 1B); depositing a deformable conductive material (150) to at least partially fill the pattern of passages (ink 150, an electroconductive paste, is coated over the screen printing plate, paragraph [0043]); removing the removable stencil from the surface of the substrate layer to leave a first pattern of deformable conductive material formed on the substrate layer (Figures 2C – 2D), wherein the first pattern of deformable conductive material can (claim merely recites “can” --- thus, there is no actual requirement for the pattern of deformable conductive material to comprise at least one gap) comprise at least one gap (157, Figure 2D and Figure 3); covering at least a portion of the first pattern of deformable conductive material with a first stacked layer, wherein the first stacked layer is an insulation layer, an encapsulation layer, or a combination thereof: and unitizing the circuit assembly, wherein unitizing the circuit assembly causes the at least one gap to heal (Figure 2D --- also, see 112 rejection). Iwase does not specifically disclose covering at least a portion of the first pattern of deformable conductive material with a stacked layer, such as an insulation layer.
However, covering a conductive pattern/layer of a circuit board with insulating material is quite common and well known in the art for such things as preventing short circuits, managing heat, and providing structural support, and is merely a design option for a skilled artisan without the exercise of inventive skill.
Regarding claim 2, Iwase discloses wherein the pattern of passages comprises a trace feature having a trace width, a trace flare feature having a trace flare width, a staggered pattern of trace flare features, a tab having a tab width, a via feature having a via diameter, or a combination thereof (Figures 2A – 2D).
Regarding claim 3, Iwase discloses wherein the deformable conductive material comprises a viscosity, and wherein the viscosity is optimized such that the deformable conductive material heals upon the unitization but not such that the deformable conductive material overly deforms and does not achieve an intended pattern (Figures 2A – 2D).
Regarding claim 4, Iwase discloses wherein an adhesive characteristic of the deformable conductive material, a viscosity of the deformable conductive material, or a combination thereof are optimized such that the deformable conductive material remains on the substrate layer upon removal of the removable stencil and does not adhere to the pattern of passages of the removable stencil thereby lifting the deformable conductive material off of the substrate layer (Figures 2A – 2D).
Regarding claim 5, Iwase discloses wherein unitizing the circuit assembly comprises heating at least a portion of the circuit assembly (Figures 2A – 2D).
Regarding claim 6, Iwase discloses wherein unitizing the circuit assembly comprises applying pressure to at least one surface of the circuit assembly (Figures 2A – 2D).
Regarding claim 7, Iwase discloses providing at least one opening in the first stacked layer, the substrate layer, or a combination thereof (Figures 2A – 2D).
Regarding claim 8, Iwase discloses after covering the at least a portion of the first pattern of deformable conductive material with the first stacked layer, placing the removable stencil on the first stacked layer, repeating the steps of depositing the deformable conductive material and removing the removable stencil to form a second pattern of deformable conductive material on the first stacked layer, and covering at least a portion of the second pattern of deformable conductive material with a second stacked layer (Figures 2A – 2D).
Regarding claim 9, Iwase discloses unitizing the circuit assembly including the substrate layer, the first stacked layer, and the second stacked layer, wherein the unitizing causes at least one gap of the second pattern of deformable conductive material to heal (Figures 2A – 2D).
Regarding claim 10, Iwase discloses after covering at least a portion of the second pattern of deformable conductive material with the second stacked layer, placing the removable stencil on the second stacked layer, repeating the steps of depositing the deformable conductive material and removing the removable stencil to form a third pattern of deformable conductive material on the second stacked layer, and covering at least a portion of the third pattern of deformable conductive material with a third stacked layer (Figures 2A – 2D).
Regarding claim 11, Iwase discloses unitizing the circuit assembly including the substrate layer, the first stacked layer, the second stacked layer, and the third stacked layer, wherein the unitizing causes at least one gap of the third pattern of deformable conductive material to heal (Figures 2A – 2D).
Regarding claim 12, Iwase discloses after covering at least a portion of the third pattern of deformable conductive material with the third stacked layer, repeating the steps of placing the removable stencil, depositing the deformable conductive material, removing the removable stencil, and covering at least a portion of the resulting pattern of deformable conductive material until a desired number of layers has been achieved (Figures 2A – 2D).
Regarding claim 13, Iwase discloses unitizing the circuit assembly including the desired number of layers (Figures 2A – 2D).
Regarding claim 14, Iwase discloses attaching an electrical component to the substrate layer or the first stacked layer (Figures 2A – 2D).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to TREMESHA W BURNS whose telephone number is (571)270-3391. The examiner can normally be reached Monday-Friday 8am - 4:30 pm EST.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Timothy Thompson can be reached at (571) 272-2342. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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TREMESHA W. BURNS
Primary Examiner
Art Unit 2847
/TREMESHA W BURNS/Primary Examiner, Art Unit 2847