DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of the Application
Claims 1-23 are pending in this application.
Information Disclosure Statement
The information disclosure statements (IDS) submitted on 8/30/2023 and 9/17/2023 and 3/19/2026 are being considered by the examiner.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 7-10, 13, 17-20 and 23 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Grande (US 6085967 A, IDS)
Re Claim 7 Grande teaches a system on a wafer (SoW) assembly (10, FIG. 1, col 3 line 29) comprising:
a first SoW assembly structure (18, col 5 line 9) having a first coefficient of thermal expansion (col 5 line 12 states, “In silicon wafers it is preferable to plasma etch first locating features 22, 24, and 26.” This implies 18 is silicon),
the first SoW assembly structure (18) including a first slot (22, col 5 line 9) at a first location, a second slot (26) at a second location, and a third slot (24) at a third location; and
a second SoW assembly structure (12, col 7 line 39) stacked on the first SoW assembly structure (18, FIG. 2), the second SoW assembly structure (12, col 4 line 42 states, “Assembly jig 10 is preferably constructed of materials selected from the group consisting of aluminum…” 12 is constructed of aluminum as 10 is aluminum and the non 12 part is silicon) having a second coefficient of thermal expansion (12 is aluminum, NPL Material Expansion Coefficients shows on table 17-1 on page 2 aluminum coefficient of expansion is 23.6 ppm per degrees Celsius) that is different than the first coefficient of thermal expansion (18 is silicon, NPL Material Expansion Coefficients shows on table 17-10 on page 10 silicon coefficient of expansion is 5.0 ppm per degrees Celsius), the second SoW assembly structure (12) having a first pin extending therefrom (14, col 7 line 13) and at least partially disposed in the first slot (22, FIG. 2, col 5 line 9), a second pin (14) extending therefrom and at least partially disposed in the second slot (26), and a third pin (14) extending therefrom and at least partially disposed in the third slot (24),
wherein the first slot (22) and the second slot (26) are shaped so as to allow the first pin (14) and the second pin to move along a first axis in a plane, and the third slot (24) is shaped so as to allow the third pin (14) to move along a second axis in the plane, the second axis being different from the first axis (see modified GIF. 1 below claim 1).
Re Claim 8 Grande teaches the SoW assembly of Claim 7, wherein the first SoW (18) assembly structure is stacked with a SoW (12, FIG. 1 and 2).
Re Claim 9 Grande teaches the SoW assembly of Claim 7, wherein the second coefficient of thermal expansion (value for aluminum, see claim 7) is greater than the first coefficient of thermal expansion (value for silicon, see claim 7).
Re Claim 10 Grande teaches the SoW assembly of Claim 7, wherein the first SoW (18) assembly structure comprises a SoW (10, FIG. 1 and 2).
Re Claim 13 Grande teaches the SoW assembly of Claim 7, wherein the first axis and the second axis are substantially perpendicular to each other (See modified FIG.1 below claim 1).
Re Claim 17 Grande teaches the SoW assembly of Claim 7, wherein the first SoW assembly structure (18) includes no more than three slots (22, 26, and 24, FIG. 1) that are configured to receive pins (114) that extend from the second SoW assembly structure (12, FIG. 1 and 2).
Re Claim 18 Grande teaches a wafer (FIG. 1 and 2, 18, col 5 line 9) with an alignment structure for aligning the wafer with an element (12, col 7 line 39) stacked vertically on the wafer, the wafer comprising:
a first slot (22, col 5 line 9) formed at a first location of the wafer (18), the first slot configured to mate with a first pin (14, col 7 line 13) and to align the wafer (18) and the element (12) along a first axis, the first slot (22) shaped to allow the wafer (18) to move along the first axis when the first slot (22) and the first pin (14) are mated (FIG. 1 and 2);
a second slot (26, col 5 line 9) formed at a second location of the wafer (18) different from the first location, the second slot (26) configured to mate with a second pin (14) and to align the wafer (18) and the element (12) along the first axis (FIG. 1 and 2); and
a third slot (24, col 5 line 9) formed at a third location of the wafer (18) different from the first and second locations, the third slot (24) configured to mate with a third pin (14) and to align the wafer (18) and the element (12) along a second axis different from the first axis (See modified FIG. 1 below claim 1).
Re Claim 19 Grande teaches the wafer of Claim 18, wherein the wafer (18 is silicon, NPL Material Expansion Coefficients shows on table 17-10 on page 10 silicon coefficient of expansion is 5.0 ppm per degrees Celsius) comprises a material that has a coefficient of thermal expansion that is lower than a coefficient of thermal expansion of a material of the element (12 is aluminum, NPL Material Expansion Coefficients shows on table 17-1 on page 2 aluminum coefficient of expansion is 23.6 ppm per degrees Celsius).
Re Claim 20 Grande teaches the wafer of Claim 18, wherein the first axis and the second axis are substantially perpendicular to each other (see modified FIG. 1 below claim 1).
Re Claim 23 Grande teaches the wafer of Claim 18, wherein the wafer (18) comprises a plurality of integrated circuit dies (20, FIG. 1, col 6 line 27 “predetermined patterns of device components 20”).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-2, 5, and 16 are rejected under 35 U.S.C. 103 as being unpatentable over Grande (US 6085967 A, IDS) in view of Davis et al. (US 20150327394 A1, IDS).
Re Claim 1 Grande teaches a system on a wafer (SoW) assembly (10, FIG. 1, col 3 line 29) comprising:
a first SoW assembly structure (18, col 5 line 9) including a first slot (22, col 5 line 9) at a first location, a second slot (26) at a second location, and a third slot (24) at a third location; and
a second SoW assembly structure (12, col 7 line 39) stacked with the first SoW assembly structure (18), the second SoW assembly structure (12) having a first pin (14, col 7 line 13) extending there from and at least partially disposed in the first slot (22, FIG. 2), a second pin (14) extending therefrom and at least partially disposed in the second slot (26), and a third pin (14) extending therefrom and at least partially disposed in the third slot (24), and
wherein the first slot (22) and the second slot (26) are shaped so as to allow the first pin (14) and the second pin (14) to move along a first axis in a plane, and the third slot (24) is shaped so as to allow the third pin (14) to move along a second axis in the plane that is different from the first axis.
See modified FIG. 1 below for labelled parts
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Grande does not teach the first SoW assembly structure or the second SoW assembly structure is included in a thermal system that is configured to cool a SoW.
Davis teaches the second SoW assembly structure (20) is included in a thermal system ([0030] “The pin fin heatsink 20 is aligned above the board 70 so that the heatsink covers all of the components 72, 74, 76 that are to be cooling with the heatsink.”) that is configured to cool a SoW (70, [0031], FIG. 1).
It would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching as taught by Davis into the structure of Grande since Davis teaches a structure with a wafer cooling system.
The ordinary artisan would have been motivated to modify Davis in combination with Grande in the above manner for the motivation of integrating a cooling system to the structure to ensure the device does not over heat and is able to function optimally. [0005] states, “A heat sink may be disposed on an electronic component to conduct heat generated by the electronic component through the heat sink to a plurality of air-cooled fins to remove heat from the electronic component by dissipation to surrounding air flow.”
Re Claim 2 Grande teaches the SoW assembly of Claim 1, wherein the first SoW assembly (18) structure comprises the SoW (18, col 5 line 9).
Grande does not teach the second SoW assembly structure comprises a heat dissipation structure.
Davis teaches the second SoW assembly ([0030] “The pin fin heatsink 20 is aligned above the board 70 so that the heatsink covers all of the components 72, 74, 76 that are to be cooling with the heatsink.”) structure comprises a heat dissipation structure (FIG. 1).
It would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching as taught by Davis into the structure of Grande since Davis teaches a structure with a wafer cooling system.
The ordinary artisan would have been motivated to modify Davis in combination with Grande in the above manner for the motivation of integrating a cooling system to the structure to ensure the device does not over heat and is able to function optimally. [0005] states, “A heat sink may be disposed on an electronic component to conduct heat generated by the electronic component through the heat sink to a plurality of air-cooled fins to remove heat from the electronic component by dissipation to surrounding air flow.”
Re Claim 5 Grande in view of Davis teaches the SoW assembly of Claim 1, wherein the first axis is substantially perpendicular to the second axis (see modified Grande FIG. 1 below claim 1).
Re Claim 16 Grande teaches the SoW assembly of Claim 7, but does not teach the second SoW assembly structure comprises a heat dissipation structure.
Davis teaches the second SoW assembly structure comprises a heat dissipation structure (FIG. 1).
It would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching as taught by Davis into the structure of Grande since Davis teaches a structure with a wafer cooling system.
The ordinary artisan would have been motivated to modify Davis in combination with Grande in the above manner for the motivation of integrating a cooling system to the structure to ensure the device does not over heat and is able to function optimally. [0005] states, “A heat sink may be disposed on an electronic component to conduct heat generated by the electronic component through the heat sink to a plurality of air-cooled fins to remove heat from the electronic component by dissipation to surrounding air flow.”
Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over Grande (US 6085967 A, IDS) in view of Davis et al. (US 20150327394 A1, IDS) as applied to claims 1-2 above, and further in view of Miley (US 5949244 A).
Re Claim 3 Grande in view of Davis teaches the SoW assembly of Claim 2, but does not teach a reinforcement feature coupled to the SoW, wherein the reinforcement feature comprises an opening that aligns with the first slot, wherein a size of the opening is smaller than a size of the first slot such that the reinforcement feature impedes the first pin from physically contacting the SoW.
Miley teaches a reinforcement feature (1305, col 14 line 27) coupled to the SoW (1300, col 7 line 16, the structure 1300 will be attached to a wafer during manufacturing, col 1 line 32 states, “Distinct semiconductor integrated circuits or microchips (or chips) are generally manufactured on a single wafer of semiconductor material.”), wherein the reinforcement feature (1305) comprises an opening that aligns with the first slot (broader opening in 1300 around 1305 in FIG. 9B), wherein a size of the opening is smaller than a size of the first slot (slot is opening in 1300 around 1305 in FIG. 9B) such that the reinforcement feature (1305) impedes the first pin (1125, col 14 line 26) from physically contacting the SoW (1300, FIG. 9B-D, 750 is a probe ring col 6 line 64, 750 and 1300 are part of the same system, and the probe ring will handle a wafer. Col1 line 37 states, “While the contact pads are exposed in wafer or microchip form, which is before the microchips are packaged, a selected number of microchips are tested by automated test equipment that utilize probe rings…”).
It would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching as taught by Miley into the structure of Grande in view of Davis since Miley teaches a structure containing a reinforcement feature to align and protect parts of a wafer system.
The ordinary artisan would have been motivated to modify Miley in combination with Grande in view of Davis in the above manner for the motivation of forming reinforcement features to help align the device features. Col 14 line 23 states, “Referring to FIG. 9C, probe ring alignment plate 1300 (with probe card assembly 950 secured thereto) is mounted to probe alignment base plate 1100 via probe alignment assembly control pins 1125 and probe alignment assembly control holes 1305. This step could be used to verify alignment of probe(s) 705 to probe target holes 1275 and to determine distant offsets…”
Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Grande (US 6085967 A, IDS) in view of Davis et al. (US 20150327394 A1, IDS) and Miley (US 5949244 A) as applied to claims 1-3 above, and further in view of Han et al. (KR 20120068302 A)
Re Claim 4 Grande in view of Davis and Miley teaches the SoW assembly of Claim 3, but does not teach the opening has an oval shape.
Han teaches the opening (140, FIG. 1 and 2) has an oval shape (Page 3 par 1 states, “The alignment key holes H have a shape of one of a circle, an ellipse… A conductive film 140 is formed in each of the alignment keyholes H, and the conductive film 140 is formed to fill the alignment key holes H, respectively, or is not illustrated, but the alignment key holes are not shown. It may be formed only on the surface of the semiconductor wafer 100 exposed by the alignment keyhole H so as not to completely fill the (H).” Form 140 only on the side walls of the structure and integrating the pin 140 as taught by Han into the reinforcement feature taught by Miley will create an alignment pit that has an oval opening and is separated from the wafer).
It would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching as taught by Han into the structure of Grande in view of Davis and Miley since Han teaches a structure containing a reinforcement feature to align and protect parts of a wafer system.
The ordinary artisan would have been motivated to modify Han in combination with Grande in view of Davis and Miley in the above manner for the motivation of forming ellipse openings in the pins to optimize the packaging structure to help improve the performance of the device. Page 2 par 2 states, “Among packaging technologies of semiconductor integrated circuits, three-dimensional lamination technology has been developed with the goal of reducing the size of electronic devices, increasing the mounting density and improving the performance thereof.”
Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over Grande (US 6085967 A, IDS) in view of Davis et al. (US 20150327394 A1, IDS) as applied to claim 1 above, and further in view of Tseng et al. (US 20200381362 A1) and Chun et al. (US 20200395257 A1, IDS).
Re Claim 6 Grande in view of Davis teaches the SoW assembly of Claim 1, wherein the first (Grande, 18) and second (12) SoW assembly structures are stacked with the SoW (FIG.2).
Grande in view of Davis does not teach the first SoW assembly structure comprises a cooling system and the second SoW assembly structure comprises an input/output frame.
Tseng teaches the first SoW assembly structure (110) [0016] comprises a cooling system (152 is connected to the bottom of 110 in FIG. 5, [0024] states, “…a heat dissipation member 152… In other embodiments, the heat dissipation member may be a heat sink…”)
It would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching as taught by Tseng into the structure of Grande in view of Davis since Tseng teaches a stacked wafer system.
The ordinary artisan would have been motivated to modify Tseng in combination with Grande in view of Davis in the above manner for the motivation optimally integrating a cooling system on the first SoW to allow for the device function at a peak level and still allow for the device to not be over sized and able to be scaled down as the industry evolves. [0001] states, “With the continued evolution of semiconductor technologies, semiconductor chips/dies are becoming increasingly smaller.”
Grande in view of Davis and Tseng does not teach the second SoW assembly structure comprises an input/output frame.
Chun teaches the second SoW (100) [0022] assembly structure comprises an input/output frame (300, [0051] calls 300 a “mechanical brace”, FIG. 14. Paragraph [0040] in the enclosed application states, “The I/Oframe15 can contribute to the structural integrity of the processing system 10.”).
It would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching as taught by Chun into the structure of Grande in view of Davis and Tseng since Chun teaches a stacked wafer system.
The ordinary artisan would have been motivated to modify Chun in combination with Grande in view of Davis and Tseng in the above manner for the motivation optimally integrating an I/O frame into the wafer system structure allow for the structure to be steady and strong but also as small as possible as the industry increasingly evolves towards smaller devices. [0001] states, “As semiconductor technologies continue to evolve, integrated circuit dies are becoming increasingly smaller.”
Claims 11-12 and 22 are rejected under 35 U.S.C. 103 as being unpatentable over Grande (US 6085967 A, IDS) in view of Miley (US 5949244 A).
Re Claim 11 Grande teaches the SoW assembly of Claim 10, but does not teach a reinforcement feature coupled with the SoW.
Miley teaches a reinforcement feature (1305, col 14 line 27) coupled with the SoW (1300, col 7 line 16, FIG. 9B-D, 750 is a probe ring col 6 line 64, 750 and 1300 are part of the same system, and the probe ring will handle a wafer. Col1 line 37 states, “While the contact pads are exposed in wafer or microchip form, which is before the microchips are packaged, a selected number of microchips are tested by automated test equipment that utilize probe rings…”).
It would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching as taught by Miley into the structure of Grande since Miley teaches a structure containing a reinforcement feature to align and protect parts of a wafer system.
The ordinary artisan would have been motivated to modify Miley in combination with Grande in the above manner for the motivation of forming reinforcement features to help align the device features. Col 14 line 23 states, “Referring to FIG. 9C, probe ring alignment plate 1300 (with probe card assembly 950 secured thereto) is mounted to probe alignment base plate 1100 via probe alignment assembly control pins 1125 and probe alignment assembly control holes 1305. This step could be used to verify alignment of probe(s) 705 to probe target holes 1275 and to determine distant offsets…”
Re Claim 12 Grande in view of Mily teaches the SoW assembly of Claim 11, wherein the reinforcement feature (Miley, 1305) comprises an opening (center of 1305) that aligns with the first slot (opening in 1300 around 1305 in FIG. 9B), and a size of the opening is smaller than a size of the first slot (FIG. 9B).
Re Claim 22 Grande teaches the wafer of Claim 18, but does not teach a reinforcement feature thereon, the reinforcement feature comprising an opening that aligns with the first slot, a size of the opening of the reinforcement feature being smaller than a size of the first slot such that the reinforcement feature is configured to impede the first pin from physically contacting the wafer.
Miley teaches a reinforcement feature thereon (1305, col 14 line 27), the reinforcement feature (1305) comprising an opening (center of 1305) that aligns with the first slot (opening in 1300 around 1305 in FIG. 9B), a size of the opening (center of 1305) of the reinforcement feature being smaller than a size of the first slot (opening in 1300 where 1305 sits) such that the reinforcement feature (1305) is configured to impede the first pin (1125, col 14 line 21) from physically contacting the wafer ( FIG. 9B-D, 750 is a probe ring col 6 line 64, 750 and 1300 are part of the same system, and the probe ring will handle a wafer. Col 1 line 37 states, “While the contact pads are exposed in wafer or microchip form, which is before the microchips are packaged, a selected number of microchips are tested by automated test equipment that utilize probe rings…”).
It would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching as taught by Miley into the structure of Grande since Miley teaches a structure containing a reinforcement feature to align and protect parts of a wafer system.
The ordinary artisan would have been motivated to modify Miley in combination with Grande in the above manner for the motivation of forming reinforcement features to help align the device features. Col 14 line 23 states, “Referring to FIG. 9C, probe ring alignment plate 1300 (with probe card assembly 950 secured thereto) is mounted to probe alignment base plate 1100 via probe alignment assembly control pins 1125 and probe alignment assembly control holes 1305. This step could be used to verify alignment of probe(s) 705 to probe target holes 1275 and to determine distant offsets…”
Claims 14-15 and 21 are rejected under 35 U.S.C. 103 as being unpatentable over Grande (US 6085967 A, IDS) in view of Han et al. (KR 20120068302 A)
Re Claim 14 Grande teaches the SoW assembly of Claim 7, but does not teach the first slot comprises an oval slot configured to receive the first pin, and wherein a major axis of the oval slot of the first slot extends along the first axis.
Han teaches the first slot (H, FIG. 1) comprises an oval slot (page 3 par 4 “The alignment key holes H have a shape of one of a circle, an ellipse…”) configured to receive the first pin (140, page 3 par 4 “conductive film”), and wherein a major axis of the oval slot of the first slot extends along the first axis (see drawing below).
Modified FIG. 1 shown below
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It would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching as taught by Han into the structure of Grande since Han teaches a structure containing a reinforcement feature to align parts of a wafer system.
The ordinary artisan would have been motivated to modify Han in combination with Grande in the above manner for the motivation of forming ellipse holes to optimize the packaging structure to help improve the performance of the device. Page 2 par 2 states, “Among packaging technologies of semiconductor integrated circuits, three-dimensional lamination technology has been developed with the goal of reducing the size of electronic devices, increasing the mounting density and improving the performance thereof.”
Re Claim 15 Grande in view of Han teaches the SoW assembly of Claim 14, wherein the third slot (see drawing under claim 14) comprises an oval slot (page 3 par 4 “The alignment key holes H have a shape of one of a circle, an ellipse…”) configured to receive the third pin (140), and a major axis of the oval slot of the third slot extends along the second axis (see drawing under claim 14).
Re Claim 21 Grande teaches the wafer of Claim 18, but does not teach the first slot comprises an oval slot configured to receive the first pin, a major axis of the oval slot of the first slot extends along the first axis, the third slot comprises an oval slot configured to receive the third pin, and a major axis of the oval slot of the third slot extends along the second axis.
Han teaches the first slot (H, FIG. 1) comprises an oval slot (page 3 par 4 “The alignment key holes H have a shape of one of a circle, an ellipse…”) configured to receive the first pin (140, page 3 par 4 “conductive film”), a major axis of the oval slot of the first slot extends along the first axis (see drawing under claim 14), the third slot (see drawing under claim 14) comprises an oval slot (page 3 par 4 “The alignment key holes H have a shape of one of a circle, an ellipse…”) configured to receive the third pin (140), and a major axis of the oval slot of the third slot extends along the second axis (see drawing under claim 14).
It would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching as taught by Han into the structure of Grande since Han teaches a structure containing a reinforcement feature to align parts of a wafer system.
The ordinary artisan would have been motivated to modify Han in combination with Grande in the above manner for the motivation of forming ellipse holes to optimize the packaging structure to help improve the performance of the device. Page 2 par 2 states, “Among packaging technologies of semiconductor integrated circuits, three-dimensional lamination technology has been developed with the goal of reducing the size of electronic devices, increasing the mounting density and improving the performance thereof.”
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to KENNETH MARK SIPLING whose telephone number is (571)272-3269. The examiner can normally be reached 10 AM - 6 PM EST.
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/KENNETH MARK SIPLING/Examiner, Art Unit 2818 /DUY T NGUYEN/Primary Examiner, Art Unit 2818 4/22/26
Prosecution Insights