DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
This Office Action is in response to Applicant’s Amendment filed on March 10, 2026. Claims 1, 5, 8-14, 16-19 and 21 have been amended. No new claims have been added. Claim 6 has been canceled. Currently, claims 1-5 and 7-23 are pending.
Applicant’s amendment to claims 8-13 are successfully overcomes the 112(b) rejection of claims 8-13 set forth in the previous Office Action.
The amendment to claim 8 omits the previously recited limitation of “two dielectric regions with arbitrary thickness” without clearly indicating whether the limitation is intended to be deleted. Similarly, amendment to claim 10 omits the previously recited limitation of, “using any of a plurality of different techniques” without clearly indicating whether the limitation is intended to be deleted. Applicant is required to clearly present claim amendments in compliance with 37 CFR 1.121 such that changes to claim language are readily identifiable. Applicant is required to clarify the amendment by explicitly canceling, retaining or properly amending the limitation.
Response to Arguments
Applicant’s arguments with respect to claims 1, 5 and 8 have been considered but are moot as applied to the newly added claim limitation because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Applicant’s argument regarding claim 1 that Huang fails to teach an electric field management layer positioned between the gate terminal and the source terminal is unpersuasive. Huang discloses dielectrics 438 and 440 acting as an electric field management layer that directly covers the exposed sidewalls of the gate electrode 430 (see e.g., Para [0061], Figures 2 and 5-14).
Applicant’s argument regarding claim 5 that Huang fails to teach an electric field management layer positioned along the edge of the gate terminal is unpersuasive. Huang explicitly discloses an electric field management layer comprised of dielectrics 438 and 440 which covers the exposed sidewalls of the gate electrode 430 (see e.g., Para [0061], Figures 2 and 5-14).
Applicant’s arguments regarding claim 14 that Huang fails to teach an electric field management layer disposed on the interface between the first layer and second layer is unpersuasive. Claim 14 does not require the layer to be directly on the interface. Regardless, Huang’s electric field management layer 440 is disposed on the interface between the gate electrode 430 and the first passivation layer 420 (see e.g., Figures 2 and 5-14). Furthermore, the limitation in claim 16 requiring an additional layer between the field management layer and the gate electrode, this confirms that the broader language of claim 14 does not necessitate direct contact, supporting Examiner’s interpretation.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 11, 13 and 17 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
Regarding claim 11, the claim recites, “wherein the two dielectric regions or the semiconductor material are grown using metalorganic chemical vapor deposition, molecular-beam epitaxy or both”, there is no support for growing the dielectric or the semiconductor material using both metalorganic chemical vapor deposition, molecular-beam epitaxy in the disclosure.
Regarding claim 13, the claim recites, “each of the two dielectric regions comprises one or more of a binary oxide, nitrides, doped oxide, a semiconductor material, a ferroelectric, a complex oxide, a layered material or a graded composition of any of the said materials” which does not have support in the disclosure. The two dielectric regions include the passivation layer and the electric field management layer. The disclosure explicitly limits this listing of materials to only the electric field management layer not the passivation layer.
Regarding claim 17, the claim recites, “wherein the device comprises at least one of a MOSFET, JFET, multi-channel JFET, CAVET, FinFET, Trench CAVET, trench MOSFET, HEMT, MIS HEMT, Fin channel HEMT, Multi-channel HEMT, or Gate injector transistor”, however multi-channel JFET is not disclosed or supported by the disclosure.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 14-17 and 19-23 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Huang et al. (US 2014/0264360 A1; hereafter Huang).
Regarding claim 14, Huang teaches a semiconductor device (see e.g., Figures 2 and 5-14) comprising:
a first layer (see e.g., first passivation layer 420, Para [0054], Figures 2 and 5-14);
a second layer disposed on the first layer and forming an interface between the first layer and the second layer; and (see e.g., the gate electrode 430 disposed on the first passivation layer 420. This placement forms an interface where the gate electrode 430 and the first passivation layer 420 meet, Para [0058], Figures 2 and 5-14)
an electric field management layer disposed on the interface (see e.g., the second dielectric layer 440 disposed on the interface between the first passivation layer 420 and the gate electrode 430, Figures 2 and 5-14), the electric field management layer having a higher dielectric constant than that of the first or second layer to reduce a peak electric field forming at the interface (see e.g., The dielectric constant of the second dielectric layer 440 made of materials for example, Al.sub.2O.sub.3 (dielectric constant typically 8 to 10) would be higher than the first passivation layer 420 made of materials for example, SiO.sub.2 (dielectric constant typically 3.9). The second dielectric layer finely tunes the electric field adjacent to the gate 430, thus further improving the breakdown voltage, RF stability, RF linearity, and/or gain, Paras [0034], [0035], [0061], [0062], Figures 2 and 5-14).
Regarding claim 15, Huang, as referred in claim 14, further teaches
wherein the first layer comprises a terminal of the semiconductor device (see e.g., the first passivation layer 420 comprises the source and drain electrodes, Para [0057], Figures 2 and 4-15).
Regarding claim 16, Huang, as referred in claim 14, further teaches
further comprising fourth layer disposed between the electric field management layer and the first layer, between the electric field management layer and the second layer, or both, (see e.g., first dielectric layer 438 disposed between the gate electrode 430 and the second dielectric layer 440, between the first passivation layer 420 and the second dielectric layer 440, Figures 2 and 4-15) the fourth layer comprising a material that has a lower permittivity than the permittivity of the electric field management layer (see e.g., The dielectric constant of the first dielectric layer 438 made of material for example, Al.sub.2O.sub.3 (dielectric constant typically 8 to 10) would be lower than the second dielectric layer 440 made of materials for example, lanthanum oxide having a dielectric constant in the range 25-30, zirconium dioxide about 22-25, hafnium dioxide about 18-25, Paras [0034], [0035], [0061], [0062], Figures 2 and 5-14)).
Regarding claim 17, Huang, as referred in claim 14, further teaches
wherein the device comprises at least one of a MOSFET, JFET, multi-channel JFET, CAVET, FinFET, Trench CAVET, Trench MOSFET, HEMT, MIS HEMT, Fin channel HEMT, Multi-channel HEMT, or Gate injector transistor (see e.g., devices maybe laterally diffused metal oxide semiconductor (LDMOS), HEMT, MESFET, MISFET or MOSFET devices, Paras [0017], [0059], Figures 2 and 5-14).
Regarding claim 19, Huang, as referred in claim 14, further teaches
wherein the electric field management layer comprises one or more of: a binary oxide, nitrides, a doped oxide, a semiconductor material, a ferroelectric, a complex oxide, a layered material or a graded composition of any of the said materials (see e.g., The second dielectric layer 440 is an aluminum-based dielectric (e.g., Al.sub.2O.sub.3 or AlN) or a hafnium-based dielectric (e.g., HfO.sub.2), though other oxides, silicates or aluminates of zirconium, aluminum, lanthanum, strontium, tantalum, titanium and combinations thereof may also be used, including but not limited to Ta.sub.2O.sub.5, ZrO.sub.2, TiO.sub.2, Y.sub.2O.sub.3, La.sub.2O.sub.3, HfSiO.sub.X, ZrSiO.sub.X, ZrHfOx, LaSiO.sub.X, YSiO.sub.X, ScSiO.sub.X, CeSiO.sub.X, HfLaSiO.sub.X, HfAlO.sub.X, ZrAlO.sub.X, and LaAlO.sub.X. In addition, multi-metallic oxides for example, barium strontium titanate, BST, Paras [0034], [0035], [0061], [0062], Figures 2 and 5-14).
Regarding claim 20, Huang, as referred in claim 14, further teaches
wherein the electric field management layer has a dielectric constant between about 9 and about 1000 (see e.g., the materials listed for second dielectric layer 440 such as lanthanum oxide has a dielectric constant in the range 25-30, zirconium dioxide about 22-25, aluminum oxide 8-10, hafnium dioxide about 18-25).
Regarding claim 21, Huang, as referred in claim 14, further teaches
wherein the electric field management layer comprises one or more gaps (see e.g., the second dielectric layer 440 as shown in Figure 14 is disposed only on a portion of first dielectric layer 438 and has gaps or openings, Para [0035], Figures 2 and 4-15).
Regarding claim 22, Huang, as referred in claim 14, further teaches
wherein a portion of the electric field management layer forms a spacer between the first and second layers (see e.g., a portion of the second dielectric layer 440 between the first passivation layer 420 and the gate electrode 430 forms a spacer, Figures 2, and 4-15).
Regarding claim 23, Huang, as referred in claim 14, further teaches
wherein the first and second layers comprise terminals of the semiconductor device (see e.g., the gate electrode 430 and the first passivation layer comprises the source and drain electrodes 428, Figures 2 and 4-15).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-5, 7-13 and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Huang et al. (US 2014/0264360 A1; hereafter Huang) in view of Xia et al. (US 2017/0018617 A1; hereafter Xia).
Regarding claim 1, Huang teaches a semiconductor device with electric field management (see e.g., Figures 2, 5-14), the semiconductor device comprising:
a substrate (see e.g., epitaxial substrate layer 414 may be implemented with gallium nitride (GaN) and/or aluminum nitride (AlN), or any alloys such as aluminum gallium nitride (AlGaN), indium gallium nitride (InGaN), aluminum indium gallium nitride (AlInGaN), or silicon carbide (SiC), Para [0052], Figures 2 and 5-14) having a drift region (see e.g., the embodiments described can be applied to devices such as laterally diffused metal oxide semiconductor (LDMOS) transistors or GaN transistors such as hetero junction field effect transistor (HFET). These transistors have drift regions, Paras [0017], [0032], Figures 2 and 5-14);
a dielectric passivation layer disposed on the drift region, the dielectric passivation layer having a dielectric constant (see e.g., first passivation layer 420 is formed with any desired insulating or dielectric material, such as Si.sub.3N.sub.4 (silicon nitride), SiO.sub.2, SiO.sub.xN.sub.y, AlN, Al.sub.2O.sub.3, and/or other suitable combinations or mixtures thereof disposed on the drift region of for example, a laterally diffused metal oxide semiconductor (LDMOS) transistors or GaN field effect transistor, Paras [0017], [0054], Figures 2 and 5-14);
a gate terminal disposed on the dielectric passivation layer; and (see e.g., a mushroom or T-shaped gate electrode 430 disposed on the first passivation layer 420, Para [0058], Figures 2 and 5-14)
a source terminal disposed..; and (see e.g., source contact 428, Para [0057], Figures 2 and 5-15)
an electric field management layer having a dielectric constant which is higher than the dielectric constant of the dielectric passivation layer, the electric field management layer (see e.g., electric field management layer including the first dielectric layer 438 and the second dielectric layer 440.
The electric field management layer finely tunes the electric field adjacent to the gate 430, thus further improving the breakdown voltage, RF stability, RF linearity, and/or gain.
The second dielectric layer 440 may remain to cover the first dielectric layer 438 or portions of the first dielectric layer 438 in some embodiments.
The first dielectric layer 438 may be formed with any desired insulating or dielectric material (e.g., Si.sub.3N.sub.4, SiO.sub.2, SiO.sub.xN.sub.y, AlN, Al.sub.2O.sub.3, and/or other suitable combinations or mixtures thereof.
The second dielectric layer 440 is an aluminum-based dielectric (e.g., Al.sub.2O.sub.3 or AlN) or a hafnium-based dielectric (e.g., HfO.sub.2), though other oxides, silicates or aluminates of zirconium, aluminum, lanthanum, strontium, tantalum, titanium and combinations thereof may also be used, including but not limited to Ta.sub.2O.sub.5, ZrO.sub.2, TiO.sub.2, Y.sub.2O.sub.3, La.sub.2O.sub.3, HfSiO.sub.X, ZrSiO.sub.X, ZrHfOx, LaSiO.sub.X, YSiO.sub.X, ScSiO.sub.X, CeSiO.sub.X, HfLaSiO.sub.X, HfAlO.sub.X, ZrAlO.sub.X, and LaAlO.sub.X. In addition, multi-metallic oxides (for example barium strontium titanate, BST).
The dielectric constant of the first dielectric layer 438 and the second dielectric layer 440 made of materials for example, Al.sub.2O.sub.3 (dielectric constant typically 8 to 10) would be higher than the first passivation layer 420 made of materials for example, SiO.sub.2 (dielectric constant typically 3.9), Paras [0034], [0035], [0061], [0062], Figures 2 and 5-14) disposed over the dielectric passivation layer (see e.g., electric field management layer including the first dielectric layer 438 and the second dielectric layer 440 disposed over the first passivation layer 420, Paras [0034], [0035], [0061], [0062], Figures 2 and 5-14) and between the source terminal and the gate terminal (see e.g., electric field management layer including the first dielectric layer 438 and the second dielectric layer 440 disposed between the source contact 428 and the gate electrode 430, Figures 2 and 5-14)
Huang does not explicitly teach
“a source terminal disposed above the gate terminal”;
In a similar field of endeavor Xia teaches
a source terminal disposed above the gate terminal (see e.g., source ohmic contact 210 disposed above the gate 230/234/232, Para [0056], Figure 2);
Therefore, it would have been obvious to one skilled in the art at the time the invention was effectively to implement Xia’s teachings of a source terminal disposed above the gate terminal in the device of Huang as since such an arrangement represents a routine design choice and a predictable variation for achieving the known structural configuration.
Regarding claim 2, Huang, as modified by Xia, teaches the limitations of claim 1 as mentioned above. Huang further teaches
the electric field management layer is disposed over the dielectric passivation layer so as to form a junction with the dielectric passivation layer at a location substantially proximate to a peak electric field within the semiconductor device (see e.g. electric field management layer including the first dielectric layer 438 and the second dielectric layer 440 disposed over the first passivation layer 420 forms a junction with the first passivation layer 420 at a location substantially proximate to the peak electric field within the semiconductor device. By positioning the electrical field management layer at this critical location, the device finely tunes the electric field adjacent to the gate 430, thus further improving the breakdown voltage, RF stability, RF linearity, and/or gain, Para [0034], Figures 2 and 5-14).
Regarding claim 3, Huang, as modified by Xia, teaches the limitations of claim 2 as mentioned above. Huang further teaches
wherein the junction is formed at a three- way junction of the dielectric passivation layer, the electric field management layer, and the gate terminal (see e.g., the electric field management layer including the first dielectric layer 438 and the second dielectric layer 440 disposed over the first passivation layer 420 and the gate electrode 430. This placement forms a three-way junction where the first passivation layer 438, the electric field management layer and the gate electrode 430 meet, Figures 2 and 5-14).
Regarding claim 4, Huang, as modified by Xia, teaches the limitations of claim 2 as mentioned above. Huang further teaches
further comprising a gate dielectric layer disposed between the gate terminal and the dielectric passivation layer (see e.g., one or more gate insulator layers (e.g., silicon dioxide, Al.sub.2O.sub.3, HfO.sub.2) may be deposited over the gate contact surface and over surface passivation layer 420 to form MISFET or MOSFET devices, Paras [0058], [0059], Figures 2 and 5-14).
Regarding claim 5, Huang teaches a semiconductor device (see e.g., Figures 2 and 5-14) comprising:
an electric field management layer formed from a first material (see e.g., electric field management layer including the first dielectric layer 438 and the second dielectric layer 440.
The electric field management layer finely tunes the electric field adjacent to the gate 430, thus further improving the breakdown voltage, RF stability, RF linearity, and/or gain.
The second dielectric layer 440 may remain to cover the first dielectric layer 438 or portions of the first dielectric layer 438 in some embodiments.
The first dielectric layer 438 may be formed with any desired insulating or dielectric material (e.g., Si.sub.3N.sub.4, SiO.sub.2, SiO.sub.xN.sub.y, AlN, Al.sub.2O.sub.3, and/or other suitable combinations or mixtures thereof.
The second dielectric layer 440 is an aluminum-based dielectric (e.g., Al.sub.2O.sub.3 or AlN) or a hafnium-based dielectric (e.g., HfO.sub.2), though other oxides, silicates or aluminates of zirconium, aluminum, lanthanum, strontium, tantalum, titanium and combinations thereof may also be used, including but not limited to Ta.sub.2O.sub.5, ZrO.sub.2, TiO.sub.2, Y.sub.2O.sub.3, La.sub.2O.sub.3, HfSiO.sub.X, ZrSiO.sub.X, ZrHfOx, LaSiO.sub.X, YSiO.sub.X, ScSiO.sub.X, CeSiO.sub.X, HfLaSiO.sub.X, HfAlO.sub.X, ZrAlO.sub.X, and LaAlO.sub.X. In addition, multi-metallic oxides (for example barium strontium titanate, BST, Paras [0034], [0035], [0061], [0062], Figures 2 and 5-14);
wherein the electric field management layer is disposed over a dielectric passivation layer formed from a second, different material (see e.g., the electric field management layer is disposed on a first passivation layer 420 formed with any desired insulating or dielectric material, such as Si.sub.3N.sub.4 (silicon nitride), SiO.sub.2, SiO.sub.xN.sub.y, AlN, Al.sub.2O.sub.3, and/or other suitable combinations or mixtures thereof. The first passivation layer 420 maybe made of material for example, SiO.sub.2 while the first and second dielectric layers 438 and 440 respectively maybe made of a different material for example, Al.sub.2O.sub.3, Paras [0017], [0054], Figures 2 and 5-14), with the dielectric passivation layer having a dielectric constant which is lower than the dielectric constant of the electric field management layer (see e.g., The dielectric constant of the first dielectric layer 438 and the second dielectric layer 440 made of materials for example, Al.sub.2O.sub.3 (dielectric constant typically 8 to 10) would be higher than the first passivation layer 420 made of materials for example, SiO.sub.2 (dielectric constant typically 3.9), Paras [0034], [0035], [0061], [0062], Figures 2 and 5-14).
a gate terminal disposed on the dielectric passivation layer (see e.g., a mushroom or T-shaped gate electrode 430 disposed on the first passivation layer 420, Para [0058], Figures 2 and 5-14), wherein the electric field management layer is disposed along an edge of the gate terminal; and (see e.g., electric field management layer including the first dielectric layer 438 and the second dielectric layer 440 covers the exposed sidewall surfaces of the gate electrode 430, Para [0061], Figures 2 and 5-14)
a source terminal disposed …. . (see e.g., source contact 428, Para [0057], Figures 2 and 5-15)
Huang does not explicitly teach
“a source terminal disposed above the gate terminal, wherein the source terminal is disposed on the electric field management layer”.
In a similar field of endeavor Xia teaches
a source terminal disposed above the gate terminal (see e.g., source ohmic contact 210 disposed above the gate 230/234/232, Para [0056], Figure 2), wherein the source terminal is disposed on the electric field management layer (see e.g., the source ohmic contact 210 disposed above the dielectric 240 formed of materials such as aluminum oxide (Al.sub.2O.sub.3), aluminum nitride (AlN), Paras [0055], [0056], [0058], Figure 2).
Therefore, it would have been obvious to one skilled in the art at the time the invention was effectively to implement Xia’s teachings of a source terminal disposed above the gate terminal, wherein the source terminal is disposed on the electric field management layer in the device of Huang as since such an arrangement represents a routine design choice and a predictable variation for achieving the known structural configuration.
Regarding claim 7, Huang, as modified by Xia, teaches the limitations of claim 5 as mentioned above. Huang further teaches
further comprising a gate region (see e.g., a mushroom or T-shaped gate electrode 430, Para [0058], Figures 2 and 5-14), a source region and a drain region (see e.g., source/drain contacts 428, Para [0060], Figures 2 and 5-14) and wherein the electric field management layer is disposed adjacent to the gate terminal (see e.g., the electric field management layer including first dielectric layer 438 and the second dielectric layer 440 is disposed adjacent to the gate electrode 430, Figures 2 and 5-14), wherein a dielectric passivation layer, electric field management layer, and gate terminal form a three-way junction (see e.g., the electric field management layer including the first dielectric layer 438 and the second dielectric layer 440 disposed over the first passivation layer 420 and the gate electrode 430. This placement forms a three-way junction where the first passivation layer 438, the electric field management layer and the gate electrode 430 meet, Figures 2 and 5-14).
Regarding claim 8, Huang teaches a semiconductor structure (see e.g., Figures 2 and 5-14) comprising:
at least one semiconductor region that includes a semiconductor material (see e.g., epitaxial substrate layer 414 implemented with gallium nitride (GaN) and/or aluminum nitride (AlN), or any alloys such as aluminum gallium nitride (AlGaN), indium gallium nitride (InGaN), aluminum indium gallium nitride (AlInGaN), or silicon carbide (SiC). These materials are semiconductor compounds with strong chemical bonds that produce a wide, direct bandgap that provides high breakdown field strength. The wafer structure may also include an additional undoped or doped Al.sub.XGa.sub.1-XN barrier layer 416 formed on the epitaxial substrate layer 414 and a GaN cap layer 418, Para [0052], Figures 2 and 5-14);
two dielectric regions (see e.g., first passivation layer 420 formed with any desired insulating or dielectric material, such as Si.sub.3N.sub.4 (silicon nitride), SiO.sub.2, SiO.sub.xN.sub.y, AlN, Al.sub.2O.sub.3, and/or other suitable combinations or mixtures thereof.
Electric field management layer including the first dielectric layer 438 and the second dielectric layer 440.
The first dielectric layer 438 may be formed with any desired insulating or dielectric material (e.g., Si.sub.3N.sub.4, SiO.sub.2, SiO.sub.xN.sub.y, AlN, Al.sub.2O.sub.3, and/or other suitable combinations or mixtures thereof.
The second dielectric layer 440 is an aluminum-based dielectric (e.g., Al.sub.2O.sub.3 or AlN) or a hafnium-based dielectric (e.g., HfO.sub.2), though other oxides, silicates or aluminates of zirconium, aluminum, lanthanum, strontium, tantalum, titanium and combinations thereof may also be used, including but not limited to Ta.sub.2O.sub.5, ZrO.sub.2, TiO.sub.2, Y.sub.2O.sub.3, La.sub.2O.sub.3, HfSiO.sub.X, ZrSiO.sub.X, ZrHfOx, LaSiO.sub.X, YSiO.sub.X, ScSiO.sub.X, CeSiO.sub.X, HfLaSiO.sub.X, HfAlO.sub.X, ZrAlO.sub.X, and LaAlO.sub.X. In addition, multi-metallic oxides for example, barium strontium titanate, BST, Paras [0034], [0035], [0061], [0062], [0017], [0054], Figures 2 and 5-14), in contact with the semiconductor material (see e.g., the first passivation layer 420 and the electric field management layer are in contact with the GaN epitaxial substrate layer 414, barrier layer 416 and the cap layer 418, Paras [0052], [0053], Figures 2 and 5-14), the semiconductor material having one or more terminals, (see e.g., the source and drain electrodes 428 and the gate electrode 430, Figures 2 and 5-14) and with one of the dielectric regions having a relative permittivity which is higher than a relative permittivity of the other one of the dielectric regions, (see e.g., The first passivation layer 420 maybe made of material for example, SiO.sub.2 while the first and second dielectric layers 438 and 440 respectively maybe made of a different material for example, Al.sub.2O.sub.3. The dielectric constant of the first dielectric layer 438 and the second dielectric layer 440 made of materials for example, Al.sub.2O.sub.3 (dielectric constant typically 8 to 10) would be higher than the first passivation layer 420 made of materials for example, SiO.sub.2 (dielectric constant typically 3.9), Paras [0017], [0054], Figures 2 and 5-14) wherein at least one dielectric region of the two dielectric regions is disposed along an edge of a first terminal of the one or more terminals (see e.g., electric field management layer including the first dielectric layer 438 and the second dielectric layer 440 covers the exposed sidewall surfaces of the gate electrode 430 and the source/drain contacts 428, Para [0061], Figures 2 and 5-14) and between the first terminal and a second terminal, and (see e.g., electric field management layer including the first dielectric layer 438 and the second dielectric layer 440 disposed between the source contact 428 and the gate electrode 430, Figures 2 and 5-14)
wherein the relative permittivity of the at least one dielectric region is higher than the semiconductor material (see e.g., if the epitaxial substrate is made of for example, GaN it has a dielectric constant of around 8.9 which would be lower than the dielectric constant of the electric field management layer made of for example, Al.sub.2O.sub.3 which has a dielectric constant typically 8 to 10).
Huang does not explicitly teach
“wherein the second terminal is disposed above the first terminal;”
In a similar field of endeavor Xia teaches
wherein the second terminal is disposed above the first terminal (see e.g., source ohmic contact 210 disposed above the gate 230/234/232, Para [0056], Figure 2);
Therefore, it would have been obvious to one skilled in the art at the time the invention was effectively to implement Xia’s teachings of wherein the second terminal is disposed above the first terminal in the device of Huang as since such an arrangement represents a routine design choice and a predictable variation for achieving the known structural configuration.
Regarding claim 9, Huang, as modified by Xia, teaches the limitations of claim 8 as mentioned above. Huang further teaches
wherein the semiconductor material is any of GaN, SiC, GaxOy, diamond, silicon, GaAs, InAlN, AlGaN, c-BN, h- BN, MoS2, MoSe2, MoTe2, WS2, WSe2, or WTe2 (see e.g., epitaxial substrate layer 414 implemented with gallium nitride (GaN) and/or aluminum nitride (AlN), or any alloys such as aluminum gallium nitride (AlGaN), indium gallium nitride (InGaN), aluminum indium gallium nitride (AlInGaN), or silicon carbide (SiC), Para [0052], Figures 2 and 5-14)
Regarding claim 10, Huang, as modified by Xia, teaches the limitations of claim 8 as mentioned above. Huang further teaches
wherein the two dielectric regions and/or semiconductor material are grown and/or deposited (see e.g., the epitaxial substrate layer 414 is formed on surface of substrate by, for example, Metal-Organo Chemical Vapor Deposition (MOCVD), Molecular Beam Epitaxy (MBE), or Hydride Vapor Phase Epitaxy (HVPE). undoped or doped Al.sub.XGa.sub.1-XN barrier layer 416 formed on the epitaxial substrate layer 414 using any desired technique (e.g., MOCVD, MBE, HVPE, or the like). GaN cap or surface termination layer 418 formed on the barrier layer 416 using any desired technique (e.g., MOCVD, MBE, HVPE, or the like).
The first passivation layer 420 maybe formed by low-pressure chemical vapor deposition (LPCVD), plasma enhanced chemical vapor deposition (PECVD), physical vapor deposition (PVD), atomic layer deposition (ALD), evaporation, sputtering or other well-known techniques.
The second dielectric layer 440 maybe formed using deposition technique (e.g., conformal CVD, PECVD, PVD, ALD, hot wire-CVD (HWCVD), catalytic CVD (CAT-CVD), electron-cyclotron resonance CVD (ECR-CVD), inductively coupled plasma CVD (ICP-CVD), evaporation, sputtering, etc.), Paras [0052], [0053], [0054], [0061], Figures 2 and 5-14).
Regarding claim 11, Huang, as modified by Xia, teaches the limitations of claim 8 as mentioned above. Huang further teaches
wherein the two dielectric regions or the semiconductor material are grown using metalorganic chemical vapor deposition, molecular-beam epitaxy or both (see e.g., the epitaxial substrate layer 414 is formed on surface of substrate by, for example, Metal-Organo Chemical Vapor Deposition (MOCVD), Molecular Beam Epitaxy (MBE), or Hydride Vapor Phase Epitaxy (HVPE). Undoped or doped Al.sub.XGa.sub.1-XN barrier layer 416 formed on the epitaxial substrate layer 414 using any desired technique (e.g., MOCVD, MBE, HVPE, or the like). GaN cap or surface termination layer 418 formed on the barrier layer 416 using any desired technique (e.g., MOCVD, MBE, HVPE, or the like), Para [0052], [0053], Figures 2 and 5-14).
Regarding claim 12, Huang, as modified by Xia, teaches the limitations of claim 8 as mentioned above. Huang further teaches
wherein each of the two dielectric regions or semiconductor material are deposited using atomic layer deposition, sputtering, chemical vapor deposition or spin-casting (see e.g., The first passivation layer 420 maybe formed by low-pressure chemical vapor deposition (LPCVD), plasma enhanced chemical vapor deposition (PECVD), physical vapor deposition (PVD), atomic layer deposition (ALD), evaporation, sputtering or other well-known techniques.
The second dielectric layer 440 maybe formed using deposition technique (e.g., conformal CVD, PECVD, PVD, ALD, hot wire-CVD (HWCVD), catalytic CVD (CAT-CVD), electron-cyclotron resonance CVD (ECR-CVD), inductively coupled plasma CVD (ICP-CVD), evaporation, sputtering, etc.), Paras [0054], [0061], Figures 2 and 5-14).
Regarding claim 13, Huang, as modified by Xia, teaches the limitations of claim 8 as mentioned above. Huang further teaches
wherein each of the two dielectric regions comprises one or more of: a binary oxide, nitrides, doped oxide, a semiconductor material, a ferroelectric, a complex oxide, a layered material, or a graded composition of any of the said materials (see e.g., Electric field management layer including the first dielectric layer 438 and the second dielectric layer 440.
The first dielectric layer 438 may be formed with any desired insulating or dielectric material (e.g., Si.sub.3N.sub.4, SiO.sub.2, SiO.sub.xN.sub.y, AlN, Al.sub.2O.sub.3, and/or other suitable combinations or mixtures thereof.
The second dielectric layer 440 is an aluminum-based dielectric (e.g., Al.sub.2O.sub.3 or AlN) or a hafnium-based dielectric (e.g., HfO.sub.2), though other oxides, silicates or aluminates of zirconium, aluminum, lanthanum, strontium, tantalum, titanium and combinations thereof may also be used, including but not limited to Ta.sub.2O.sub.5, ZrO.sub.2, TiO.sub.2, Y.sub.2O.sub.3, La.sub.2O.sub.3, HfSiO.sub.X, ZrSiO.sub.X, ZrHfOx, LaSiO.sub.X, YSiO.sub.X, ScSiO.sub.X, CeSiO.sub.X, HfLaSiO.sub.X, HfAlO.sub.X, ZrAlO.sub.X, and LaAlO.sub.X. In addition, multi-metallic oxides for example, barium strontium titanate, BST, Paras [0034], [0035], [0061], [0062], [0017], [0054], Figures 2 and 5-14).
Claim 18 is rejected under 35 U.S.C. 103 as being unpatentable over Huang et al. (US 2014/0264360 A1; hereafter Huang) in view of Rahman et al. (US 2021/0296510 A1; hereafter Rahman).
Regarding claim 18, Huang, as referred in claim 14, does not explicitly teach
“wherein the device comprises at least one of a: Schottky diode, TMBS, JBS, PN diode, MPS, Trench MPS, Fin diode, multi-channel diode”.
In a similar field of endeavor Rahman teaches
wherein the device comprises at least one of a: Schottky diode, TMBS, JBS, PN diode, MPS, Trench MPS, Fin diode, multi-channel diode (see e.g., Figure 1 shows a Schottky barrier diode (SBD) with a dielectric barrier layer 130 forming an interface with the anode 140/cathode 160. A high-k dielectric 150 disposed near the interface such that the interface will determine high breakdown voltage, Para [0027]).
Therefore, it would have been obvious to one skilled in the art at the time the invention was effectively filed to implement Rahman’s teachings of wherein the device comprises at least one of a: Schottky diode, TMBS, JBS, PN diode, MPS, Trench MPS, Fin diode, multi-channel diode in the device of Huang in order to address a known problem in power electronics that is managing high electric fields to prevent device breakdown.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/FAKEHA SEHAR/ Examiner, Art Unit 2893
/YARA B GREEN/ Supervisor Patent Examiner, Art Unit 2893
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