DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed. For example, a more descriptive title could be, “DISPLAY PANEL AND DISPLAY DEVICE WITH ANODE OVERLAPPING PLANARIZING PORTION”.
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Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-8, 10-12, 20, 22 and 23 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Ma et al. (US 2022/0045155 A1; hereinafter, “Ma”).
Regarding claims 1-8, 10, 11, 20 and 23:
re claim 1, Ma discloses (in Figs. 1 and 10) a display panel, comprising:
a base substrate 710 [0065] comprising a display region (Fig. 1, region comprising elements 220) and a peripheral region (Fig. 1, edge/bezel region around elements 220);
a first planarization layer 750 (Fig. 10 and [0064]) located on one side of the base substrate 710;
a plurality of sub-pixels 771/772/773 (Fig. 10) located at the display region, wherein a plurality of anodes 771 [0069] of the plurality of sub-pixels is located on one side of the first planarization layer 750 away from the base substrate 710;
a pixel defining layer 760 (Fig. 10 and [0064]) located on one side of the first planarization layer 750 and the plurality of anodes 771 away from the base substrate 710, and having a plurality of pixel openings (e.g., opening in 760 located above 771 in Fig. 10) in one-to-one correspondence with the plurality of anodes 771, wherein each of the plurality of pixel openings exposes at least a part of an anode 771 corresponding to each of the plurality of pixel openings; and
a planarization structure 300/3001 (Figs. 10 and [0069, 0071]) comprising a plurality of planarization portions 300/3001 located at the display region, the plurality of planarization portions being located between the base substrate 710 and the first planarization layer 750 and covered by the first planarization layer 750, and the plurality of planarization portions being in one-to-one correspondence with a first group of pixel openings (Fig. 10), wherein the first group of pixel openings comprise at least a part of the plurality of pixel openings, an orthographic projection of each of the first group of pixel openings on the base substrate is a first orthographic projection (see “1” in Exhibit A above), orthographic projections of an anode and a planarization portion which correspond to each of the first group of pixel openings on the base substrate are a second orthographic projection (see “2” in Exhibit A) and a third orthographic projection (see “3” in Exhibit A) respectively, and an overlapping portion (see “overlapping portion of…” in Exhibit A above) of the first orthographic projection and the second orthographic projection is located within the third orthographic projection;
re claim 2, the display panel according to claim 1, further comprising:
a second planarization layer 730 (Fig. 10 and [0064]) located between the first planarization layer 750 and the base substrate 710, wherein the plurality of planarization portions 300/3001 is located between the first planarization layer 750 and the second planarization layer 730;
wherein each of the plurality of sub-pixels further comprises:
a pixel driving circuit comprising a driving transistor, the driving transistor
comprising a gate 723 (Fig. 10 and [0064]), a first electrode (“1st electrode” in Exhibit A) and a second electrode (“2nd electrode” in Exhibit A), wherein the first electrode and the second electrode are covered by the second planarization layer 730, and a metal portion (“metal” in Exhibit A) located between the first planarization layer 750 and the second planarization layer 730, wherein the metal portion is connected to the anode 771 via a first via hole penetrating through the first planarization layer 750 and connected to the first electrode via a second via hole penetrating through the second planarization layer 730;
re claim 3, the display panel according to claim 2, wherein the plurality of planarization portions 300/3001 is located in a same layer as the metal portion (“metal” in Exhibit A);
re claim 4, the display panel according to claim 3, further comprising a plurality
of data lines (e.g., Vdata in Fig. 6, which is connected to drive transistor T0) configured to provide a data signal to the plurality of sub-pixels, each of the plurality of data lines comprising:
a first data portion (Vdata in Fig. 6) located at the display region and located in a same layer as the first electrode (i.e., located at least “in” layer 750, which is above source/drain metal layer 727 in Fig. 10); and
a second data portion located at the peripheral region (i.e., data line portions inherently extend into the peripheral region, e.g., see US 2019/0348491 to Chung et al., Fig. 3 and [0094], wherein DL extends into a peripheral region), connected to the first data portion and located in a same layer as the metal portion (i.e., located at least “in” layer 750, which is above “metal” in Exhibit A);
re claim 5, the display panel according to claim 3, further comprising:
a plurality of second power lines V1 (Fig. 6 and [0056]) configured to provide a second power signal to the plurality of sub-pixels, wherein a voltage of the second power signal V1 (Fig. 6) is greater than a voltage of a first power signal V2 (Fig. 6) provided to a cathode of the plurality of sub-pixels (e.g., in Fig. 6, the light-emitting device 50 represent a sub-pixel), and the plurality of second power lines is located in a same layer as the first electrode (i.e., in Fig. 6, “V1” connects to source/drain of transistor T5, which is connected to the anode of LED 50; accordingly, V1 is located in a same layer as the first electrode or source/drain electrode);
re claim 6, the display panel according to claim 1, further comprising:
a plurality of signal lines (e.g., scan lines S3 in Fig. 6 and [0056]) configured to provide a signal to the plurality of sub-pixels, wherein at least one planarization portion of the plurality of planarization portions is arranged in a same layer as one of the plurality of signal lines and connected to the one of the plurality of signal lines (i.e., scan lines S3 connect to the gate of T5, wherein the gate of T5 would be gate 723 in Fig. 10; accordingly, at least one planarization portion 300 and on signal line S3 are arranged at least “in” layer 750, which is above both the portion 300 and gate 723 in Fig. 10);
re claim 7, the display panel according to claim 6, wherein the plurality of signal lines (scan line S3 or in Fig. 10, one of the source/drain electrode 727) extends along a first direction (into the page as view in Fig. 10), and a minimum length of the at least one
planarization portion 300 in a second direction (horizontal direction as view in Fig. 10) is greater than a maximum length of the one of the plurality of signal lines in the second direction, wherein the first direction is perpendicular to the second direction (i.e., in Fig. 10, the length of 300 in the horizontal direction is larger than the length of 727 in the horizontal direction);
re claim 8, the display panel according to claim 6, wherein the plurality of signal lines comprises:
a data line configured to provide a data signal to the plurality of sub-pixels; or
a second power line V1 (Fig. 6) configured to provide a second power signal to the plurality of sub-pixels (element 50 in Fig. 6), wherein a voltage of the second power signal V1 is greater than a voltage of the a first power signal V2 (Fig. 6) provided to a cathode of the plurality of sub-pixels;
re claim 10, the display panel according to claim 1, wherein an area of the overlapping portion (see “overlapping portion…” in Exhibit A) of the first orthogonal projection and the second orthogonal projection is smaller than an area of the third orthogonal projection (see “3”in Exhibit A);
re claim 11, the display panel according to claim 1, further comprising:
a first power line 7733 (Fig. 14 and [0082]) located at the peripheral region (e.g., outside of “101” in Fig. 14) and configured to provide a first power signal to a cathode 7731 [0082] of the plurality of sub-pixels; and
a conductive structure comprising at least one conductive portion 7732 (Fig. 14 and [0082]) located at the display region (e.g., “101” in Fig. 14), wherein the at least one conductive portion 7732 is configured such that a part of current flowing from the plurality of anodes 771 (Fig. 14 and [0069]) to the first power line 7733 via the cathode 7731 flows back to the first power line 7733 via the at least one conductive portion 7732;
re claim 20, the display panel according to claim 11, wherein the at least one conductive portion comprises a plurality of conductive portions connected to each other, and each of the plurality of conductive portions is reused as one of the plurality of planarization portions (i.e., in Fig. 16, a plurality of pixels requires a plurality of conductive portions 7735/7736 [0083] connected to each other with the cathode signal line [0083]); and
re claim 23, the a display device 1000 (Fig. 22 and [0092], comprising the display panel according claim 1.
Therefore, claims 1-8, 10, 11, 20 and 23 are anticipated by Ma.
Regarding claim 12:
Ma discloses a display panel, comprising:
a base substrate 710 (Fig. 16) comprising a display region 101 (Figs. 15-16) and a peripheral region (outside 101 in Figs. 15-16);
a plurality of sub-pixels (e.g., pixels comprising 7731 in Figs. 15-16) located at the display region 101;
a first power line 7733 (Figs. 15-16) located at the peripheral region and configured to provide a first power signal to a cathode 7731 of the plurality of sub-pixels; and
a conductive structure comprising at least one conductive portion 7735 (Fig. 16) located at the display region 101, wherein the at least one conductive portion is configured such that a part of current flowing from a plurality of anodes 771 (Fig. 16) of the plurality of sub-pixels to the first power line 7733 via the cathode 7731 flows back to the first power line 7733 via the at least one conductive portion 7735.
Therefore, Ma anticipates claim 12.
Regarding claim 22:
Ma discloses a display panel, comprising:
a base substrate 710 (Fig. 16) comprising a display region 101 (Figs. 15-16) and a peripheral region (outside 101 in Figs. 15-16);
a plurality of sub-pixels (e.g., pixels comprising 7731 in Figs. 15-16) located at the display region 101;
a first power line 7733 (Figs. 15-16) located at the peripheral region and configured to provide a first power signal to a cathode 7731 of the plurality of sub-pixels; and
a conductive structure comprising at least one conductive portion 7735 (Fig. 16) located at the display region 101, wherein the at least one conductive portion is connected to the first power line 7733 via a first connection line and connected to the first power line via a second connection line (i.e., in Fig. 16, the one conductive portion 7735 is connected to the power line 7733 using two connection lines in two separate vias).
Therefore, Ma anticipates claim 22.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 21 is/are rejected under 35 U.S.C. 103 as being unpatentable over Ma in view of Wang et al. (US 2016/0161776 A1; hereinafter, “Wang”).
Regarding claim 21:
Ma anticipates claim 11 and further discloses wherein a material of the at least one conductive portion 7732 (and 300 in Fig. 14) is [transparent] material [0043], each of the at least one conductive portion 7732 (Fig. 14) is located between a pixel driving circuit of a corresponding sub-pixel of the plurality of sub-pixels and the base substrate (i.e., the pixel driving circuit includes cathode wiring line 7731/7733; accordingly, portion 7732 is between line 7731/7733 and substrate 710 in Fig. 14), and an
orthographic projection of each of the at least one conductive portion 7732 (Fig. 14) on the base substrate 710 at least partially overlaps with an orthographic projection of the pixel driving circuit (e.g., orthographic projection of “7731/7733” in Fig. 14) of the corresponding sub-pixel on the base substrate.
Ma does not disclose the conductive portion 7732 is light-shielding material. However, Wang teaches, in a similar device (Fig. 2F and [0029]), a conductive portion 320 of a common electrode can be transmissive or reflective (i.e., light shielding).
It would have been obvious to one of ordinary skill in the art to modify Ma by specifically incorporating light-shielding material for conductive portion 7732, because Wang teaches such a conductive portion can be either transparent (as in Ma) or light-shielding, wherein incorporating a specific type of material would depend on a particular design requirement, e.g., incorporating a light-shielding (or reflective) material would direct light in the upward direction of Ma’s display device.
Allowable Subject Matter
Claims 13-16 and 18 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Claims 13-16 and 18 are allowed because the prior art of record cannot anticipate or render obvious the limitations in claim 13 (when combined with claim 12), and claims 14-16 and 18 depend from claim 13.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. The references listed on the attached PTO-892 disclose display panel comprising planarization structures having some similarity to that of the current invention.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to LEX H MALSAWMA whose telephone number is (571)272-1903. The examiner can normally be reached M-F (4-12 Hours, between 5:30AM-10PM).
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, N. Drew Richards can be reached at 571-272-1736. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/LEX H MALSAWMA/Primary Examiner, Art Unit 2892