Prosecution Insights
Last updated: May 29, 2026
Application No. 18/549,372

FLIP CONNECTION STRUCTURE, ROOM-TEMPERATURE FLIP CONNECTION STRUCTURE, AND CONNECTION METHOD THEREFOR

Final Rejection §102§103
Filed
Sep 07, 2023
Priority
Mar 18, 2021 — JP 2021-045132 +1 more
Examiner
MCCOY, THOMAS WILSON
Art Unit
2814
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Sony Semiconductor Solutions Corporation
OA Round
2 (Final)
93%
Grant Probability
Favorable
3-4
OA Rounds
7m
Est. Remaining
99%
With Interview

Examiner Intelligence

Grants 93% — above average
93%
Career Allowance Rate
13 granted / 14 resolved
+24.9% vs TC avg
Moderate +12% lift
Without
With
+12.5%
Interview Lift
resolved cases with interview
Typical timeline
3y 4m
Avg Prosecution
23 currently pending
Career history
56
Total Applications
across all art units

Statute-Specific Performance

§103
75.9%
+35.9% vs TC avg
§102
12.0%
-28.0% vs TC avg
§112
5.6%
-34.4% vs TC avg
Black line = Tech Center average estimate • Based on career data from 14 resolved cases

Office Action

§102 §103
Attorney Docket Number: SYP332914US01 Filing Date: 9/07/2023 Claimed Foreign Priority Date: 3/18/2021 (JP2021-045132) Inventors: Terahata et al. Examiner: Thomas McCoy DETAILED ACTION This Office action responds to the application filed on 9/07/2023. Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for a rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. Claim Interpretation Claim 2 recites the limitation “…a configuration in which one of the semiconductors is formed by an aluminum bump and another one of the semiconductors is formed by an aluminum pad electrode, or a configuration in which both of the semiconductors are formed by the aluminum bump…”, which will be interpreted as “…a configuration in which one of the semiconductor terminals is formed by an aluminum bump and another one of the semiconductor terminals is formed by an aluminum pad electrode, or a configuration in which both of the semiconductor terminals are formed by the aluminum bumps…” for the purpose of examination. Claim 7 recites the limitation “…the semiconductor is joined to the substrate at room temperature”, which will be interpreted as “…the semiconductor is joined to the substrate of a stacked display-based panel at room temperature” for purpose of examination. Claim Rejections - 35 USC § 102 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claim 1 is rejected under 35 U.S.C. 102(a)(1) as being anticipated by Chen (US 20210225727 A1). Regarding claim 1, Chen (see, e.g., fig. 8) shows all aspects of the instant invention, including: a flip-chip connection structure (e.g., package structure PK4) in which semiconductors (e.g., core portion 202 + paragraph 65 “…the core portion 202 may be a substrate such as a bulk semiconductor substrate” + paragraph 79 “The conductive terminals 230 may be used to bond to an external device or an additional electrical component. In some embodiments, the conductive terminals 230 are used to bond to a…semiconductor substrate”), the flip chip connection structure (e.g., package structure PK4) comprising: Terminals (e.g., conductive terminals 230 + contact pads 310) that connect the semiconductors (e.g., core portion 202 + paragraph 65 “…the core portion 202 may be a substrate such as a bulk semiconductor substrate” + paragraph 79 “The conductive terminals 230 may be used to bond to an external device or an additional electrical component. In some embodiments, the conductive terminals 230 are used to bond to a…semiconductor substrate”), the terminals each being formed by aluminum (Al) (see, e.g., paragraph 79 “the conductive terminals 230 may include a conductive material such as …aluminum…”); The terminals (e.g., conductive terminals 230 + contact pads 310) being integrally joined to each other to constitute a joined body (e.g., top contact pad 310 + conductive terminal 230 + bottom contact pad 310); Claims 5-6 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Akira (JP 2003303853 A). Regarding claim 5, Akira (see, e.g., description text) shows all aspects of the instant invention, including a room temperature flip-chip connection structure in which: a semiconductor is connected to a substrate to be used in a liquid crystal panel (see, e.g., paragraph text “substrates … in the manufacturing process of flat display panels such as plasma displays, semiconductor chips…are mounted on the substrate…”) to be used in a liquid crystal panel (see, e.g., paragraph text “substrates(for example, liquid crystal, EL…)…”) or an organic EL panel of a display system, wherein the semiconductor is joined and formed to a substrate of at least one of the liquid crystal panel and the organic EL panel at room temperature (see, e.g., paragraph text “…the recognition means is used to align the chip and the substrate, and the ultrasonic bonding means applies ultrasonic vibration to the contacting portions of both electrodes of the substrate and the chip to bond them. When ultrasonic vibration is applied to the contact portion of both electrodes of the substrate and the chip, the heat generated is at room temperature…” + paragraph text “The “chip” in the present invention means, for example… a semiconductor chip…” + note the substrate can include the liquid crystal embodiment, see previous paragraph text); Regarding claim 6, Akira (see, e.g., description text) shows joining at the room temperature is performed by functions of an ultrasonic wave (see, e.g., paragraph text “the present inventor has focused on bonding both electrodes of the chip and the substrate by ultrasonic waves”) and pressurizing force (see, e.g., paragraph text “the chip and the substrate are heated and temporarily pressure-bonded to bond Temporary pressure bonding step A2”). Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim 2 is rejected under 35 U.S.C. 103 as being unpatentable over Chen in view of Tsai (US 20220293524 A1). Regarding claim 2, Chen (see, e.g., fig. 8) shows the joined body (e.g., top contact pad 310 + conductive terminal 230 + bottom contact pad 310) includes a configuration in which one of the semiconductor terminals (e.g., terminal 230 of core portion 202) is formed by an aluminum bump (see, e.g., paragraph 79 “…the conductive terminals 230 include …C4 bumps, bumps…the conductive terminals 230 may include a conductive material such as …aluminum…”) and another one of the semiconductor (e.g., semiconductor of paragraph 79) terminals (e.g., contact pad 310) is formed by a pad electrode (see, e.g., contact pad 310 + note contact pad 310 is connected to semiconductor mentioned in paragraph 79). Chen (see, e.g., fig. 8), however, fails to show that this semiconductor terminal formed by a pad electrode is aluminum. Tsai (see, e.g., fig. 1A), in a similar device to Chen, teaches a contact pad (e.g., second contact pad 122) comprising aluminum (paragraph 27 “The second contact pads 122 may include, or may consist of, a conductive material such as aluminum…”). Accordingly, it would have been obvious to one of ordinary skill in the art at the time of filing the invention to include the aluminum of Tsai within the contact pad of Chen, as aluminum was a well-known material to be included within a contact pad, as taught by Tsai. Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over Chen in view of Tsai further in view of Stansbury (US 6001724 A). Regarding claim 3, Chen in view of Tsai fails to teach the aluminum bump includes either of: the aluminum bump formed by a wire bonder using an aluminum wire, or an aluminum bump formed in a wedge shape by being joined onto a pad electrode at room temperature using the aluminum wire. Stansbury (see, e.g., paragraph 14), in a similar device to Chen in view of Tsai, teaches a bump formed by a wire bonder using an aluminum wire (see, e.g., paragraph 14 “The method, simply stated, comprises: providing a semiconductor die having a pad, providing an aluminum wire; forming a ball bump on the aluminum wire using a thermosonic ball bonding apparatus…”). Accordingly, it would have been obvious to one of ordinary skill in the art at the time of filing the invention to include the ball bonding method of Stansbury within the aluminum bump forming of Chen in view of Tsai, as this wire ball-bonding method was a well-known technique at the time of filing the invention in order to form a bump on a conductive pad, as taught by Stansbury. Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Chen (hereinafter, Chen1) in view of Tsai further in view of Chen (US 9646943 B1)(hereinafter Chen2). Regarding claim 4, Chen1 in view of Tsai fails to teach the aluminum pad electrode includes either of: an aluminum pad electrode having a configuration in which a pad electrode is grown in a thickness direction of the pad electrode by an aluminum wire, or an aluminum pad electrode having a configuration in which a pad electrode having a thick film shape is formed by sputtering or vapor deposition during manufacturing of a wafer. Chen2 (see, e.g., fig. 8B), in a similar device to Chen1 in view of Tsai, teaches an aluminum contact pad (e.g., contact pad 803 + paragraph 23 “The contact pads 803 may comprise a conductive material such as aluminum…”) having a thick film shape (e.g., note shape of contact pad 803 in fig. 8B) is formed by vapor deposition (see, e.g., paragraph 23 “…may be formed over using, for example, physical vapor deposition (PVD)…”). Accordingly, it would have been obvious to one of ordinary skill in the art at the time of filing the invention to include the vapor deposition step of Chen2 within the pad electrode forming step of Chen1 in view of Tsai, as this vapor deposition technique was a well-known technique at the time of filing the invention in order to form a pad electrode, as taught by Chen2. Claim 7 is rejected under 35 U.S.C. 103 over Akira in view of Visani (US 20200348576 A1). Regarding claim 7, Akira fails to show the substrate includes a substrate of a stacked display-panel, and the semiconductor is joined to the substrate at room temperature. Visani (see, e.g., fig. 1A), in a similar device to Akira, teaches a substrate (e.g., substrate 150) includes a stacked display-panel (e.g., stack of displays 101, 102, 103, 104, 105, 106). Accordingly, it would have been obvious to one of ordinary skill in the art at the time of filing the invention to include the stacked display-panel of Visani within the substrate of Akira, in order to increase the reliability of the display panel setup, as providing more than one display panel decreases the risk of device failure due to single display-panel degradation. Note that Akira teaches joining a semiconductor to the substrate at room temperature (see rejection of claim 5), and it would have been obvious to one of ordinary skill in the art to further join this new substrate of a stacked display-panel to the semiconductor, in order to provide an electrical connection to the stacked display-panels. Claim 8 is rejected under 35 U.S.C. 103 over Chen1 in view of Tsai further in view of Akira. Regarding claim 8, Chen1 (see, e.g., fig. 8) shows most aspects of the instant invention including a flip-chip connection method comprising: Forming semiconductors (e.g., core portion 202 + paragraph 65 “…the core portion 202 may be a substrate such as a bulk semiconductor substrate” + paragraph 79 “The conductive terminals 230 may be used to bond to an external device or an additional electrical component. In some embodiments, the conductive terminals 230 are used to bond to a…semiconductor substrate”) by joining the semiconductors (e.g., core portion 202 + paragraph 65 “…the core portion 202 may be a substrate such as a bulk semiconductor substrate” + paragraph 79 “The conductive terminals 230 may be used to bond to an external device or an additional electrical component. In some embodiments, the conductive terminals 230 are used to bond to a…semiconductor substrate”) to each other by a flip chip connection method using a joined body (e.g., top contact pad 310 + conductive terminal 230 + bottom contact pad 310) joined by an aluminum bump (e.g., terminal 230 + paragraph 79 “…the conductive terminals 230 include …C4 bumps, bumps…the conductive terminals 230 may include a conductive material such as …aluminum…”) and a pad electrode (see, e.g., contact pad 310 + note contact pad 310 is connected to semiconductor mentioned in paragraph 79). Chen1 (see, e.g., fig. 8), however, fails to show the pad electrode is aluminum and that when joining a flip chip is performed, joining by weighting or pressurization and an ultrasonic wave in an environment of room temperature in any step. Tsai (see, e.g., fig. 1A), in a similar device to Chen, teaches a contact pad (e.g., second contact pad 122) comprising aluminum (paragraph 27 “The second contact pads 122 may include, or may consist of, a conductive material such as aluminum…”). Accordingly, it would have been obvious to one of ordinary skill in the art at the time of filing the invention to include the aluminum of Tsai within the contact pad of Chen, as aluminum was a well-known material to be included within a contact pad, as taught by Tsai. Chen1 in view of Tsai, however, fails to teach when joining a flip chip is performed, joining by weighting or pressurization and an ultrasonic wave in an environment of room temperature in any step. Akira (see, e.g., description text), in a similar device to Chen1 in view of Tsai, teaches joining by pressurization (see, e.g., paragraph text “the chip and the substrate are heated and temporarily pressure-bonded to bond Temporary pressure bonding step A2”) and an ultrasonic wave (see, e.g., paragraph text “the present inventor has focused on bonding both electrodes of the chip and the substrate by ultrasonic waves”) in an environment of room temperature in any step (see, e.g., paragraph text “When ultrasonic vibration is applied to the contact portion of both electrodes of the substrate and the chip, the heat generated is at room temperature or at a low temperature (for example, about 100 ° C.) in order to improve the bonding condition”). Accordingly, it would have been obvious to one of ordinary skill in the art at the time of filing the invention to include the pressurization and ultrasonic wave methodology of Akira within the method of Chen1 in view of Tsai, as pressurization and ultrasonic wave bonding were well-known techniques in the art at the time of filing the invention, in order to bond/join the conductive interface portions of the semiconductor to one another, as taught by Akira. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to Thomas McCoy at (571) 272-0282 and between the hours of 9:30 AM to 6:30 PM (Eastern Standard Time) Monday through Friday or by e-mail via Thomas.McCoy@uspto.gov. If attempts to reach the examiner by telephone are unsuccessful, the examiner's supervisor, Wael Fahmy, can be reached on (571) 272-1705. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /Thomas McCoy/ _______________________ Thomas McCoy Patent Examiner Art Unit 2814 571-272-0282 /WAEL M FAHMY/Supervisory Patent Examiner, Art Unit 2814
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Prosecution Timeline

Sep 07, 2023
Application Filed
Nov 07, 2025
Non-Final Rejection mailed — §102, §103
Feb 06, 2026
Response Filed
May 26, 2026
Final Rejection mailed — §102, §103 (current)

Precedent Cases

Applications granted by this same examiner with similar technology

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

3-4
Expected OA Rounds
93%
Grant Probability
99%
With Interview (+12.5%)
3y 4m (~7m remaining)
Median Time to Grant
Moderate
PTA Risk
Based on 14 resolved cases by this examiner. Grant probability derived from career allowance rate.

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