DETAILED ACTION
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-11, 14-15, 17 and 20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Niu et al. (Niu, US 2021/0151416).
Regarding claim 1, Niu shows a power module, comprising: a first substrate (substrate 5 in FIG. 19); a second substrate (substrate 4); a plurality of semiconductor transistor die (chip 6/7) positioned between the first substrate (substrate 5) and the second substrate (substrate 4), a bottom surface of each of the plurality of semiconductor transistor die being secured in electrical contact to at least one of the first substrate or the second substrate (see FIG. 19 with respect to Fig. 15); a plurality of power terminals (terminal 1-2 and [0064]); a plurality of terminal pins ([0086]); and a plurality of sintered-silver interposers (silver paste 16 in FIG. 15 and [0070]) bonded to a top contact of each of the plurality of semiconductor transistor die and positioned between the first substrate and the second substrate in the power module (see FIG. 15 with respect to FIG. 19).
Regarding claim 2, Niu shows a power module, comprising, wherein at least one of the first substrate (substrate 5) or the second substrate (substrate 4) comprises an insulated metal substrate (IMS) ([0064]).
Regarding claim 3, Niu shows a power module, comprising, wherein the IMS comprises a layer of ceramic or polymer between two layers of copper ([0084]).
Regarding claim 4, Niu shows a power module, comprising wherein: the IMS comprises a layer of ceramic or polymer, a first inner metal layer, and a second inner metal layer; the bottom surface of a first semiconductor transistor die among the plurality of semiconductor transistor die is bonded to the first inner metal layer using sintered silver paste (silver paste 16 in FIG. 19); and the bottom surface of a second semiconductor transistor die among the plurality of semiconductor transistor die is bonded to the second inner metal layer using sintered silver paste (silver paste 16 in FIG. 19).
Regarding claim 5, Niu shows a power module, comprising, wherein: a first power terminal (terminal 1-2) among the plurality of power terminals is electrically coupled to the first inner metal layer; and a second power terminal among the plurality of power terminals is electrically coupled to the second inner metal layer (see Fig. 19).
Regarding claim 6, Niu shows a power module, comprising, wherein: the first substrate comprises a first inner metal layer; the second substrate comprises a second inner metal layer; the bottom surface of a first semiconductor transistor die among the plurality of semiconductor transistor die is bonded to the first inner metal layer using sintered silver paste; and the bottom surface of a second semiconductor transistor die among the plurality of semiconductor transistor die is bonded to the second inner metal layer using sintered silver paste (silver paste 16 in FIG. 19).
Regarding claim 7, Niu shows a power module, comprising wherein the plurality of power terminals are staggered for electrical coupling to a busbar (see FIG. 19).
Regarding claim 8, Niu shows a power module, comprising further comprising: a first plurality of bond wires electrically coupled from a first semiconductor transistor die among the plurality of semiconductor transistor die to a first subset of the plurality of terminal pins; and a second plurality of bond wires electrically coupled from a second semiconductor transistor die among the plurality of semiconductor transistor die to a second subset of the plurality of terminal pins (see Fig. 19 and [0070-0071]).
Regarding claim 9, Niu shows a power module, comprising, wherein: the plurality of semiconductor transistor die are coupled in a half bridge configuration; and each of the plurality of semiconductor transistor die comprises a Silicon Carbide (SiC) metal oxide semiconductor field effect power transistor ([0064+]).
Regarding claim 10, Niu shows a power module, comprising, wherein the plurality of sintered-silver interposers comprise interposers cut from a bar of sintered silver paste (silver paste 16).
Regarding claim 11, Niu shows a method of manufacturing a power module (FIG. 19), comprising: applying a layer of silver paste (silver paste 16) on a metal layer of a substrate (substrate 4); positioning a plurality of semiconductor transistor die (chips 6/7) on the layer of silver paste over the metal layer of the substrate; positioning a plurality of silver interposers on the layer of silver paste over the metal layer of the substrate (see GI. 19); and heating the substrate (substrate 4/5), the plurality of semiconductor transistor die, and the plurality of silver interposers, to bond the plurality of semiconductor transistor die and a first plurality of silver interposers to the substrate (substrate 4/5).
Regarding claim 14, Niu shows a method of manufacturing a power module (FIG. 19), comprising applying a second layer of silver paste on top surface contacts of the plurality of semiconductor transistor die; and positioning a second plurality of silver interposers (silver paste 16) on the second layer of silver paste over the top surface contacts of the plurality of semiconductor transistor die (see FIG. 19).
Regarding claims 15, 17 and 20 , Niu shows a method of manufacturing a power module (FIG. 19), comprising second heating the substrate, the plurality of semiconductor transistor die, the plurality of silver interposers, and the second plurality of silver interposers, to bond the second plurality of silver interposers (silver paste 16) to the plurality of semiconductor transistor die (chips 6/7).
Allowable Subject Matter
Claims 12-13, 16 and 18-19 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ELIAS M ULLAH whose telephone number is (571)272-1415. The examiner can normally be reached M-F at 8AM-5PM EST.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Yara Green can be reached at 571-270-3035. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/ELIAS ULLAH/Primary Examiner, Art Unit 2893