DETAILED ACTION
Foreign Priority
Acknowledgment is made of applicant’s claim for foreign priority under 35 U.S.C. 119 (a)-(d). Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Claim Objections
Claims 1 and 15 are objected to because the limitation “overlaps at least two of the plurality of pixels in a plain view” should be amended to ” overlaps at least two of the plurality of pixels in a plan view” for technical accuracy and to enable limitations in dependent claims to have proper antecedent basis when referring back to the “plan view”.
Claim 2 is objected to because “gate the at least one first transistor” should be amended to “the gate of the at least one first transistor” to have proper antecedent basis.
Claim 13 is objected to because “to direction in which the gate of the at least one first transistor extends” should be amended to “to the lengthwise direction of the gate of the at least one first transistor
Claim 14 is objected to because “a pair a main electrodes” should be amended to “a pair [[a]] of main electrodes” for grammatical correctness and for better clarity.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(B) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim(s) 1-2 and 4-21 is/are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant) regards as the invention.
Claims 1 and 15 recite the limitation “wherein the at least one first transistor is included in a pixel circuit electrically coupled to at least one of the plurality of pixels and overlaps at least two of the plurality of pixels in a plain view”.
The metes and bounds of the claimed limitation can not be determined for the following reasons: the limitation is unclear grammatically whether “electrically coupled…” refers to the “at least one first transistor” or the “pixel circuit”; and the limitation is unclear grammatically whether “and overlaps at least two of the plurality of pixels in a plain view” refers to the “at least one first transistor” or the “pixel circuit”. Because the “at least one first transistor” is within the “pixel circuit”, both are possible meanings in both instances. Thus, the overall geometry required by the claim is unclear.
Claims 2 and 4-14 depend from claim 1. Claims 16-21 depend from claim 15. The dependent claims inherit the deficiencies of the claims from which they depend.
Claim Interpretations
The term “matrix arrangement direction” has not been unambiguously defined in the specification. However, the limitation “the at least one first transistor having a gate extending in a lengthwise direction inclined with respect to a matrix arrangement direction of the plurality of pixels” will be interpreted as the lengthwise direction needing to be inclined with respect to both directions that form the repetition symmetry of the matrix of the plurality of pixels. For example, the lengthwise direction would need to be inclined with respect to both the x-direction and y-direction in Applicant’s Fig. 5, as the x-direction and the y-direction make up the “matrix arrangement direction”.
This is a reasonable interpretation of the limitation given the teachings of the specification, wherein the transistors are never included with respect to only one of the x-direction and y-direction.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-2, 4-5, 7-11, 15-18, and 20-21 is/are rejected under 35 U.S.C. 103 as being unpatentable over WO 2020/059335 A1 (“Takizawa”) in view of US 2008/0315068 A1 (“Kanda”).
Regarding WO 2020/059335 A1, please see the attached copy provided by the USPTO. The document provided by the Applicant and listed on the IDS is not the document cited by WIPO and various other offices in corresponding applications. Please see the last three numbers “335”. US 2022/0037388 A1 is the corresponding US document to WO 2020/059335 A1 and is used as an English translation thereof.
Takizawa teaches, for example:
PNG
media_image1.png
661
318
media_image1.png
Greyscale
Takizawa teaches and/or would have suggested as obvious to one of ordinary skill in the art at the time of invention:
1. A solid-state imaging device (e.g. “image sensor 10”) comprising:
a first semiconductor layer (e.g. “semiconductor substrate 141” of the “first substrate 140”) including a plurality of pixels arranged in a matrix in a plane direction, each of the pixels including a photoelectric converter (e.g. “photodiode 101”); and
a second semiconductor layer (e.g. “semiconductor substrate 151” of the “second substrate 150”) stacked on the first semiconductor layer on a side opposite to a light-incident surface of the plurality of pixels, the second semiconductor layer including at least one first transistor (e.g. “pixel transistor 153”; see e.g. para 117 and Fig. 3, wherein the transistor 153 is connected to capacitor 152 via wirings, TSVs 155, etc.; see Fig. 3, wherein the device is clearly stacked and connected, and thus “on” each other; furthermore, the device may be rotated by 180 degrees leading to it meeting another interpretation of “on” being “at a higher level”).
Takizawa does not explicitly teach that the at least one first transistor is electrically coupled to the pixel, having a gate extending in a lengthwise direction inclined with respect to a matrix arrangement direction of the plurality of pixels, wherein the at least one first transistor is included in a pixel circuit electrically coupled to at least one of the plurality of pixels and overlaps at least two of the plurality of pixels in a plan view.
Kanda teaches, for example:
PNG
media_image2.png
494
579
media_image2.png
Greyscale
PNG
media_image3.png
492
508
media_image3.png
Greyscale
Kanda teaches and/or would have suggested as obvious to one of ordinary skill in the art at the time of invention, in combination with Takizawa, that the at least one first transistor is electrically coupled to the pixel, having a gate extending in a lengthwise direction inclined with respect to a matrix arrangement direction of the plurality of pixels, wherein the at least one first transistor is included in a pixel circuit electrically coupled to at least one of the plurality of pixels and overlaps at least two of the plurality of pixels in a plan view (see e.g. para 24-82, Figs. 11, 13, 14, and 16; a pixel is a unit of the imager that is symmetrically repeated in the matrix. In Fig. 1, the repeated structure appears to be confined by the lines 12 and 14 horizontally and by the lines 10 and 11 vertically. In figures 11, 13, 14, and 16, the gates overlap with, and extend beyond, these lines and thus it is reasonable to interpret that they overlap at least two pixels.).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to add the invention of Kanda to the invention of Takizawa. The motivation to do so is that the combination produces the predictable results of reducing the pitch of the circuits resulting in high density circuits (see e.g. para 15, 17, 21, 41, etc.).
Takizawa and Kanda together further teach and/or would have suggested as obvious at the time of invention to one of ordinary skill in the art:
2. The solid-state imaging device according to claim 1, wherein each of the plurality of pixels has a rectangular shape in the plan view (see e.g. shape of photodiode 101 in Fig. 13), and the gate the at least one first transistor extends in a direction parallel to a diagonal direction of each of the pixels of the plurality of pixels in the plan view (see discussion of Kanda in claim 1, see e.g. Fig. 14, wherein the diagonal orientation is visible).
4. The solid-state imaging device according to claim 3, wherein the first transistor comprises an amplifier transistor, a selection transistor, a reset transistor, or a floating diffusion conversion gain switching transistor that constitutes the pixel circuit (see e.g. para 161, wherein the pixel transistor 153 “includ[es]” reset transistor 103, switch transistor 104, amplification transistor 105, and selection transistor 106” see e.g. Fig. 2).
5. The solid-state imaging device according to claim 4, wherein when the amplifier transistor, the selection transistor, and the reset transistor are selected, a gate length of the amplifier transistor is longer than a gate length of the selection transistor or the reset transistor (see e.g. Fig. 6 of Takizawa wherein the amplifier gate 1051 had a length or width in the direction from B-to-B that is larger than the length or width of the select gate 1061 in the direction from B-to-B and larger than both the length and width of the reset gate 1031).
7. The solid-state imaging device according to claim 1, further comprising: a first terminal provided on a side of the first semiconductor layer facing the second semiconductor layer, the first terminal being electrically coupled to at least one of the plurality of pixels via a first wiring layer (see e.g. 155, connected to node 107); and
a second terminal provided on a side of the second semiconductor layer facing the first semiconductor layer (see e.g. wirings 154), the second terminal being electrically coupled to the at least one first transistor via a second wiring layer and bonded to the first terminal (insulation layers 145 and 157 have wirings therein, and all layers 141, 145, 151, 157, 162 are bonded to each other).
8. The solid-state imaging device according to claim 1, further comprising a penetrating wiring line extending through the second semiconductor layer from the first semiconductor layer and electrically coupling at least one of the plurality of pixels and the at least one first transistor (see e.g. Fig. 3, e.g. TSV 155).
9. The solid-state imaging device according to claim 3, further comprising a third semiconductor layer (e.g. “semiconductor substrate 161” in “third substrate 160”) stacked on a side opposite to the second semiconductor layer,
the third semiconductor layer including a peripheral circuit (see e.g. 164) having a second transistor and configured to control the pixel circuit (see e.g. para 120).
10. The solid-state imaging device according to claim 9, wherein the second transistor has a gate extending in a direction parallel to a matrix arrangement direction of the plurality of pixels (see e.g. Fig. 3; that the gates are parallel to the straight sides of the pixels in the matrix is the typical configuration).
11. The solid-state imaging device according to claim 1, wherein the second semiconductor layer further includes one or more elements selected from among the group consisting of a capacitor, a resistor, and a memory, the capacitor including at least one of a metal-insulator-metal capacitor and a semiconductor capacitor (see e.g. para 76-77, 115, and 172, wherein a capacitor, e.g. trench capacitor 152, may function as a second floating diffusion region to accumulate charge, thus being a “memory”).
Takizawa teaches and/or would have suggested as obvious to one of ordinary skill in the art at the time of invention:
15. An electronic apparatus, comprising: an optical system; a solid-state imaging device that receives light from the optical system (see e.g. Fig. 3),
the solid- state imaging device, including:
a first semiconductor layer (e.g. “semiconductor substrate 141” of the “first substrate 140”) including a plurality of pixels arranged in a matrix in a plane direction, each of the pixels including a photoelectric converter (e.g. “photodiode 101”); and
a second semiconductor layer (e.g. “semiconductor substrate 151” of the “second substrate 150”) stacked on the first semiconductor layer on a side opposite to a light-incident surface of the plurality of pixels, the second semiconductor layer including at least one first transistor (e.g. “pixel transistor 153”; see e.g. para 117 and Fig. 3, wherein the transistor 153 is connected to capacitor 152 via wirings, TSVs 155, etc.; see Fig. 3, wherein the device is clearly stacked and connected, and thus “on” each other; furthermore, the device may be rotated by 180 degrees leading to it meeting another interpretation of “on” being “at a higher level”); and
a signal processor that processes signals received from the solid-state imaging device (see e.g. Fig. 1, para 59-73).
Takizawa does not explicitly teach that the at least one first transistor is electrically coupled to at least one of the pixels, the at least one transistor having a gate extending in a lengthwise direction inclined with respect to a matrix arrangement direction of the plurality of pixels, wherein the at least one first transistor is included in a pixel circuit electrically coupled to at least one of the plurality of pixels and overlaps at least two of the plurality of pixels in a plan view.
Kanda teaches, for example, Figs. 1 and 14 as shown above.
Kanda teaches and/or would have suggested as obvious to one of ordinary skill in the art at the time of invention, in combination with Takizawa, that the at least one first transistor is electrically coupled to the pixel, having a gate extending in a lengthwise direction inclined with respect to a matrix arrangement direction of the plurality of pixels, wherein the at least one first transistor is included in a pixel circuit electrically coupled to at least one of the plurality of pixels and overlaps at least two of the plurality of pixels in a plan view (see e.g. para 24-82, Figs. 11, 13, 14, and 16; a pixel is a unit of the imager that is symmetrically repeated in the matrix. In Fig. 1, the repeated structure appears to be confined by the lines 12 and 14 horizontally and by the lines 10 and 11 vertically. In figures 11, 13, 14, and 16, the gates overlap with, and extend beyond, these lines and thus it is reasonable to interpret that they overlap at least two pixels.).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to add the invention of Kanda to the invention of Takizawa. The motivation to do so is that the combination produces the predictable results of reducing the pitch of the circuits resulting in high density circuits (see e.g. para 15, 17, 21, 41, etc.).
Takizawa and Kanda together further teach and/or would have suggested as obvious at the time of invention to one of ordinary skill in the art:
16. The electronic apparatus according to claim 15, wherein each of the plurality of pixels has a rectangular shape in the plan view (see e.g. shape of photodiode 101 in Fig. 13), and the gate the at least one first transistor extends in a direction parallel to a diagonal direction of each of the pixels of the plurality of pixels in the plan view (see discussion of Kanda in claim 1, see e.g. Fig. 14, wherein the diagonal orientation is visible).
17. The electronic apparatus according to claim 15, wherein the first transistor comprises an amplifier transistor, a selection transistor, a reset transistor, or a floating diffusion conversion gain switching transistor that constitutes the pixel circuit (see e.g. para 161, wherein the pixel transistor 153 “includ[es]” reset transistor 103, switch transistor 104, amplification transistor 105, and selection transistor 106” see e.g. Fig. 2).
18. The electronic apparatus according to claim 17, wherein when the amplifier transistor, the selection transistor, and the reset transistor are selected, a gate length of the amplifier transistor is longer than a gate length of the selection transistor or the reset transistor (see e.g. Fig. 6 of Takizawa wherein the amplifier gate 1051 had a length or width in the direction from B-to-B that is larger than the length or width of the select gate 1061 in the direction from B-to-B and larger than both the length and width of the reset gate 1031).
20. The electronic apparatus according to claim 15, further comprising: a first terminal provided on a side of the first semiconductor layer facing the second semiconductor layer, the first terminal being electrically coupled to at least one of the plurality of pixels via a first wiring layer (see e.g. 155, connected to node 107); and
a second terminal provided on a side of the second semiconductor layer facing the first semiconductor layer (see e.g. wirings 154), the second terminal being electrically coupled to the at least one first transistor via a second wiring layer and bonded to the first terminal (insulation layers 145 and 157 have wirings therein, and all layers 141, 145, 151, 157, 162 are bonded to each other).
21. The electronic apparatus according to claim 15, further comprising a penetrating wiring line extending through the second semiconductor layer from the first semiconductor layer and electrically coupling at least one of the plurality of pixels and the at least one first transistor (see e.g. Fig. 3, e.g. TSV 155).
Response to Arguments
Applicant's arguments with respect to the pending claims have been considered but are not persuasive. Applicant argues that Kanda does not teach “the first transistor… overlaps at least two of the plurality of pixels in a plain view” (see pages 11-12). However, a pixel is a unit of the imager that is symmetrically repeated in the matrix. In Fig. 1, the repeated structure appears to be confined by the lines 12 and 14 horizontally and by the lines 10 and 11 vertically. In figures 11 and 13, the gates overlap with, and extend beyond, these lines and thus it is reasonable to interpret that they overlap at least two pixels.
Conclusion
Conclusion / Finality
Applicant's amendment changed the scope of the claims and necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the date of this final action.
Conclusion / Prior Art
The prior art made of record, because it is considered pertinent to applicant's disclosure, but which is not relied upon specifically in the rejections above, is listed on the Notice of References Cited.
Conclusion / Contact Information
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Kevin Parendo who can be contacted by phone at (571) 270-5030 or by direct fax at (571) 270-6030. The examiner can normally be reached Monday-Friday from 9 am to 4 pm ET.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Billy Kraig, can be reached at (571) 272-8660. The fax number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/Kevin Parendo/Primary Examiner, Art Unit 2896
Prosecution Insights