DETAILED ACTION
Foreign Priority
Acknowledgment is made of applicant’s claim for foreign priority under 35 U.S.C. 119 (a)-(d). Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statements (IDS) submitted on 9/7/23, 9/12/23, 11/7/25, and 1/9/26 are in compliance with the provisions of 37 CFR 1.97 and 1.98. Accordingly, the information disclosure statement has been considered by the examiner.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The following title is suggested: Image sensor with diagonally arranged gate electrodes
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(B) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim(s) 1-14 is/are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant) regards as the invention.
Claim 1 recites the limitation “a first semiconductor layer in which a pixel is arranged in a matrix along a plane direction, the pixel including a photoelectric converter, number of the pixel being two or more”. The metes and bounds of the claimed limitation can not be determined for the following reasons: “number of the pixel being two or more” is unclear. A matrix inherently requires more than one, and the claim previously referred to only a single pixel, but now the “number of the pixel” is two or more. If “number of the pixel being two or more” refers to the total number of pixels, its redundant to the limitation about the matrix. If “number of the pixel being two or more” refers to anything else, it is not clear what it refers to.
Claims 2-14 depend from claim 1 and inherit its deficiencies.
Claim 3 recites the limitation “wherein the first transistor constitutes a pixel circuit coupled to the pixel”. Claim 4 recites the limitation “wherein the first transistor comprises an amplifier transistor, a selection transistor, a reset transistor, or a floating diffusion conversion gain switching transistor that constitutes the pixel circuit.”
The metes and bounds of the claimed limitations of claims 3 and 4 can not be determined for the following reasons: “constitute” is defined by Merriam Webster dictionary as “make up, form, compose” and the example thereof is “12 months constitute a year”. Oxford dictionary says it is “to make up, form, compose; to be the elements or material of which the thing spoken of consists”. These definitions strongly imply that the elements that “constitute” an overall thing need to fully encompass the overall thing. However, in this case, a transistor does not fully make up a pixel circuit; rather, a circuit requires at least a wiring to and from the transistor and at least another electrical element besides the transistor, because transistors can not be operated without at least applied current and voltage. Thus, it is unclear exactly what is required of this claim limitation.
Claims 4-6 and 9-10 depend from claim 3 and inherit its deficiencies. Claims 5-6 depend from claim 4 and inherit its deficiencies.
Claim 5 recites the limitation “wherein a gate length of the amplifier transistor is longer than a gate length of the selection transistor or the reset transistor”. The metes and bounds of the claimed limitation can not be determined for the following reasons: claim 4, from which claim 5 depends, requires only one of the following transistors: “an amplifier transistor, a selection transistor, a reset transistor, or a floating diffusion conversion gain switching transistor”. As such, making requirements related to plural of the transistors makes it unclear as if claim 5 actually requires more than one of the transistors or not, and referring only to the amplifier transistor and the selection or reset transistor makes it unclear if claim 5 actually requires the choice of amplifier transistor in claim 4, or not, and if claim 5 actually requires the choice of one of the reset or selection transistors in claim 4, or not.
Claim 6 recites the limitation “wherein a plurality of the amplifier transistors is electrically coupled in parallel with respect to one the pixel circuit.” The metes and bounds of the claimed limitation can not be determined for the following reasons: claim 4, from which claim 6 depends, requires only one of the following transistors: “an amplifier transistor, a selection transistor, a reset transistor, or a floating diffusion conversion gain switching transistor”. As such, making requirements related to plural of the transistors makes it unclear as if claim 6 actually requires more than one of the transistors or not, and referring only to the amplifier transistor[s] makes it unclear if claim 6 actually requires the choice of amplifier transistor in claim 4, or not.
Claim 12 recites the limitation “wherein the metal body/dielectric body/semiconductor capacitor includes a metal body as a first electrode and a semiconductor as a second electrode, the metal body having a rectangular shape in a plan view, and a centerline of the first electrode is parallel with the gate lengthwise direction of the first transistor.” The metes and bounds of the claimed limitation can not be determined for the following reasons: claim 11, from which claim 12 depends, requires “wherein one or more elements selected from among a metal body/dielectric body/semiconductor capacitor, a resistor, and a memory element are further provided in the second semiconductor layer”. As such, only one element is required. Making requirements related to the capacitor in claim 12 makes it unclear as if claim 12 actually requires the capacitor in claim 11, or not.
Claim 13 recites the limitation “wherein a resistor lengthwise direction of the resistor is parallel with the gate lengthwise direction of the first transistor”. The metes and bounds of the claimed limitation can not be determined for the following reasons: The metes and bounds of the claimed limitation can not be determined for the following reasons: claim 11, from which claim 13 depends, requires “wherein one or more elements selected from among a metal body/dielectric body/semiconductor capacitor, a resistor, and a memory element are further provided in the second semiconductor layer”. As such, only one element is required. Making requirements related to the resistor in claim 13 makes it unclear as if claim 13 actually requires the resistor in claim 11, or not.
Claim 14 recites the limitation “wherein the memory element includes paired main electrodes, a channel formation region provided between the main electrodes, a ferroelectric body provided on the channel formation region, and a gate electrode provided on the ferroelectric body, and a gate lengthwise direction of the memory element is parallel with the gate lengthwise direction of the first transistor.” The metes and bounds of the claimed limitation can not be determined for the following reasons: claim 11, from which claim 14 depends, requires “wherein one or more elements selected from among a metal body/dielectric body/semiconductor capacitor, a resistor, and a memory element are further provided in the second semiconductor layer”. As such, only one element is required. Making requirements related to the memory element in claim 14 makes it unclear as if claim 14 actually requires the memory element in claim 11, or not.
Claim Interpretation
The Office will use the following interpretations:
In claim 1, the limitation “number of the pixel being two or more” will require the matrix to require at least two pixels (which, though, it is inherent to a matrix of pixels);
In claims 3-4, the transistors will be interpreted as being in a pixel circuit;
In claim 5, the requirement about the gate lengths will not be interpreted as requiring plural transistors in claim 4, because claim 4 clearly required only one of the transistors;
In claim 6, the requirement about the plurality of amplifier transistors and their parallel arrangement will not be interpreted as requiring plural amplifier transistors in claim 4, because claim 4 clearly required only one of various options of types of transistors.
In claim 12, the requirement about the capacitor will not be interpreted as requiring the capacitor in claim 11, because claim 11 clearly required only one of a capacitor, resistor, or memory element;
In claim 13, the requirement about the resistor will not be interpreted as requiring the resistor in claim 11, because claim 11 clearly required only one of a capacitor, resistor, or memory element;
In claim 14, the requirement about the memory element will not be interpreted as requiring the memory element in claim 11, because claim 11 clearly required only one of a capacitor, resistor, or memory element.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-13 is/are rejected under 35 U.S.C. 103 as being unpatentable over WO 2020/059335 A1 (“Takizawa”) in view of US 2008/0315068 A1 (“Kanda”).
Regarding WO 2020/059335 A1, please see the attached copy provided by the USPTO. The document provided by the Applicant and listed on the IDS is not the document cited by WIPO and various other offices in corresponding applications. Please see the last three numbers “335”. US 2022/0037388 A1 is the corresponding US document to WO 2020/059335 A1 and is used as an English translation thereof.
Takizawa teaches, for example:
PNG
media_image1.png
661
318
media_image1.png
Greyscale
Takizawa teaches and/or would have suggested as obvious to one of ordinary skill in the art at the time of invention:
1. A solid-state imaging device (e.g. “image sensor 10”) comprising:
a first semiconductor layer (e.g. “semiconductor substrate 141” of the “first substrate 140”) in which a pixel is arranged in a matrix along a plane direction, the pixel including a photoelectric converter (e.g. “photodiode 101”), number of the pixel being two or more; and
a second semiconductor layer (e.g. “semiconductor substrate 151” of the “second substrate 150”) stacked on the first semiconductor layer on an opposite side to a light-incoming side of the pixel and including a first transistor (e.g. “pixel transistor 153”) (see Fig. 3, wherein the device is clearly stacked and connected, and thus “on” each other; furthermore, the device may be rotated by 180 degrees leading to it meeting another interpretation of “on” being “at a higher level”).
Takizawa does not explicitly teach the first transistor being electrically coupled to the pixel and having a gate lengthwise direction inclined with respect to an arrangement direction of the pixel.
Kanda teaches, for example:
PNG
media_image2.png
492
508
media_image2.png
Greyscale
Kanda teaches and/or would have suggested as obvious to one of ordinary skill in the art at the time of invention, in combination with Takizawa the first transistor being electrically coupled to the pixel and having a gate lengthwise direction inclined with respect to an arrangement direction of the pixel (see e.g. para 24-82, Figs. 14 and 16).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to add the invention of Kanda to the invention of Takizawa. The motivation to do so is that the combination produces the predictable results of reducing the pitch of the circuits resulting in high density circuits (see e.g. para 15, 17, 21, 41, etc.).
Takizawa and Kanda together further teach and/or would have suggested as obvious at the time of invention to one of ordinary skill in the art:
2. The solid-state imaging device according to claim 1, wherein the pixel has a rectangular shape in a plan view (see e.g. shape of photodiode 101 in Fig. 13), and the gate lengthwise direction of the first transistor is parallel with a diagonal direction of the pixel in the plan view (see discussion of Kanda in claim 1, see e.g. Fig. 14, wherein the diagonal orientation is visible).
3. The solid-state imaging device according to claim 1, wherein the first transistor constitutes a pixel circuit coupled to the pixel (see e.g. para 117 and Fig. 3, wherein the transistor 153 is connected to capacitor 152 via wirings, TSVs 155, etc.).
4. The solid-state imaging device according to claim 3, wherein the first transistor comprises an amplifier transistor, a selection transistor, a reset transistor, or a floating diffusion conversion gain switching transistor that constitutes the pixel circuit (see e.g. para 161, wherein the pixel transistor 153 “includ[es]” reset transistor 103, switch transistor 104, amplification transistor 105, and selection transistor 106” see e.g. Fig. 2).
5. The solid-state imaging device according to claim 4, wherein a gate length of the amplifier transistor is longer than a gate length of the selection transistor or the reset transistor (see claim interpretation section, above; because the claims do not positively require an amplifier transistor and/or selection/reset transistor, the limitation amounts to a hypothetical that need not be explicitly taught; however see e.g. Fig. 6 of Takizawa).
6. The solid-state imaging device according to claim 4, wherein a plurality of the amplifier transistors is electrically coupled in parallel with respect to one the pixel circuit (see claim interpretation section, above; because the claims do not positively require an amplifier transistor, the limitation amounts to a hypothetical that need not be explicitly taught).
7. The solid-state imaging device according to claim 1, further comprising: a first terminal provided on a side of the first semiconductor layer toward the second semiconductor layer, the first terminal being electrically coupled to the pixel via a first wiring layer (see e.g. 155, connected to node 107); and a second terminal provided on a side of the second semiconductor layer toward the first semiconductor layer (see e.g. wirings 154), the second terminal being electrically coupled to the first transistor via a second wiring layer and bonded to the first terminal (insulation layers 145 and 157 have wirings therein, and all layers 141, 145, 151, 157, 162 are bonded to each other).
8. The solid-state imaging device according to claim 1, further comprising a penetrating wiring line penetrating the second semiconductor layer from the first semiconductor layer to electrically couple the pixel and the first transistor to each other (see e.g. Fig. 3, e.g. TSV 155).
9. The solid-state imaging device according to claim 3, further comprising a third semiconductor layer (e.g. “semiconductor substrate 161” in “third substrate 160”) that is stacked on an opposite side of the second semiconductor layer to the first semiconductor layer and on which a peripheral circuit (see e.g. 164) is mounted, the peripheral circuit including a second transistor and controlling the pixel circuit (see e.g. para 120).
10. The solid-state imaging device according to claim 9, wherein a gate lengthwise direction of the second transistor is parallel with the arrangement direction of the pixel (see e.g. Fig. 3; that the gates are parallel to the straight sides of the pixels in the matrix is the typical configuration).
11. The solid-state imaging device according to claim 1, wherein one or more elements selected from among a metal body/dielectric body/semiconductor capacitor, a resistor, and a memory element are further provided in the second semiconductor layer (see e.g. para 76-77, 115, and 172, wherein a capacitor, e.g. trench capacitor 152, may function as a second floating diffusion region to accumulate charge, thus being a “memory”).
12. The solid-state imaging device according to claim 11, wherein the metal body/dielectric body/semiconductor capacitor includes a metal body as a first electrode and a semiconductor as a second electrode, the metal body having a rectangular shape in a plan view, and a centerline of the first electrode is parallel with the gate lengthwise direction of the first transistor (see claim interpretation section, above; because the claims do not positively require a metal body/dielectric body/semiconductor capacitor, the limitation amounts to a hypothetical that need not be explicitly taught).
13. The solid-state imaging device according to claim 11, wherein a resistor lengthwise direction of the resistor is parallel with the gate lengthwise direction of the first transistor (see claim interpretation section, above; because the claims do not positively require a resistor, the limitation amounts to a hypothetical that need not be explicitly taught).
Conclusion
Conclusion / Prior Art
The prior art made of record, because it is considered pertinent to applicant's disclosure, but which is not relied upon specifically in the rejections above, is listed on the Notice of References Cited.
Conclusion / Contact Information
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Kevin Parendo who can be contacted by phone at (571) 270-5030 or by direct fax at (571) 270-6030. The examiner can normally be reached Monday-Friday from 9 am to 4 pm ET.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Billy Kraig, can be reached at (571) 272-8660. The fax number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/Kevin Parendo/Primary Examiner, Art Unit 2896
Prosecution Insights