DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 1 – 4 is/are rejected under 35 U.S.C. 103 as being unpatentable over Drescher, US 2018/0118562.
Regarding Claim 1, Drescher teaches a stacked substrate manufacturing method, comprising: forming a bonding layer 4, which includes an oxide layer, on a surface of a second semiconductor substrate 2; bringing the oxide layer of the bonding layer into contact with a second semiconductor substrate 6, and bonding the first semiconductor substrate and the second semiconductor substrate with the bonding layer therebetween; forming, after the bonding of the first semiconductor substrate and the second semiconductor substrate, a modification layer 18 with a laser beam 20 on a first division plane along which the first semiconductor substrate is to be divided in a thickness direction thereof; thinning the first semiconductor substrate bonded to the second semiconductor substrate with the bonding layer therebetween by dividing the first semiconductor substrate starting from the modification layer formed at the first division plane in paragraphs 74 to 91 with reference to Fig. 1.
Regarding the claim, Drescher teaches forming the bonding oxide layer on the second substrate instead of the first substrate during the bonding operation.
However, it would have been obvious to one with ordinary skill in the art before the effective filing date of the claimed invention to modify Drescher and put the oxide layer on the second substrate since the purpose is to bond two wafers without having any adhesion problem.
Regarding Claim 3, Drescher fails to teach wherein the oxide layer of the bonding layer is a thermal oxide layer formed by thermally oxidizing the surface of the first semiconductor substrate.
However, it would have been obvious to one with ordinary skill in the art before the effective filing date of the claimed invention to modify Drescher and the oxide layer by thermal oxidation since thermal oxide formation is well known method in the industry.
Regarding Claim 4, Drescher teaches wherein each of the first semiconductor substrate and the second semiconductor substrate is a silicon wafer, and the oxide layer of the bonding layer is a silicon oxide layer in paragraphs 21 and 24.
Claim(s) 2 and 12 – 15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Drescher, US 2018/0118562 in view of Kanemoto, WO 2020/213479.
Drescher fails to teach the stacked substrate manufacturing method further comprising: forming a modification layer with the laser beam on a ring – shaped second division plane which is set as a periphery of the first division plane; thinning the first semiconductor substrate bonded to the second semiconductor substrate with the bonding layer therebetween and removing a bevel of the first semiconductor substrate by dividing the first semiconductor substrate starting from the modification layers formed at the first division and the second division plane.
Kanemoto teaches a feature for performing division by a step for "irradiating laser light L2 (laser light L2 for internal surface) from a laser head 110 to thereby form an internal modification layer M2 along the surface direction" (paragraph 56) and Figs. 11 – 13, the "internal modification layer M2" corresponds to the "modified layer" in the "first planned division surface" in the present invention), as well as a step for "irradiating laser light L1 (laser light L1 for periphery) from the laser head 110 to thereby form an edge modified layer M1 at the boundary between a central section Wc and a peripheral section We of a processing wafer W" (paragraph 50] and Figs. 9 and 10, the "edge modified layer M1" corresponds to the "modified layer" in the "second planned division surface" in the present invention), and a step for " dividing the processing wafer W into a first divided wafer W1 and a second divided wafer W2 while taking the edge modified layer M1 and the internal modification layer M2 as starting points" to thereby ' also remove the peripheral section We from the first divided wafer W1" (paragraph 66) and Fig. 8; the "peripheral section We" corresponds to the "bevel" in the present invention for the benefit of separating the processing target and subsequently use the separated processing target.
Therefore, it would have been obvious to one with ordinary skill in the art before the effective filing date of the claimed invention to modify Drescher and form a modification layer with the laser beam on a ring – shaped second division plane which is set as a periphery of the first division plane; thinning the first semiconductor substrate bonded to the second semiconductor substrate with the bonding layer therebetween and removing a bevel of the first semiconductor substrate by dividing the first semiconductor substrate starting from the modification layers formed at the first division and the second division plane for the benefit of separating the processing target and subsequently use the separated processing target as taught by Kanemoto.
Regarding Claim 12, "forming, by a laser beam, a modified layer on a first planned division surface that is planned to divide the laminated substrate in the thickness direction", "dividing the laminated substrate by taking as a starting point the modified layer formed on the first planned division plane", and "setting the first planned division surface inside the first semiconductor substrate, forming the modified layer on the first planned division surface, and dividing the first semiconductor substrate by taking the formed modified layer as a starting point to thereby thin the first semiconductor substrate bonded to the second semiconductor substrate with the bonding layer interposed therebetween", which are specific processing steps, are described taught by Drescher as described earlier in rejecting claim 1.
Therefore, it would have been obvious to one with ordinary skill in the art before the effective filing date of the claimed invention to modify Drescher and thereby achieve a "laminated substrate that includes a first semiconductor substrate, a bonding layer formed on the surface of the first semiconductor substrate, and a second semiconductor substrate bonded to the first semiconductor substrate with the bonding layer interposed therebetween, the bonding layer including an oxide layer that comes into contact with the second semiconductor substrate", which is a specific processing step.
Drescher fails to teach a specific configuration of a "substrate processing apparatus", but Kanemoto (Figs. 1 and 2 and locations describing same) describes a configuration of a "wafer processing system 1" (corresponding to the "substrate processing apparatus") that is provided with a "wafer conveyance region 40" provided by a "wafer conveyance apparatus 42" "configured to be able to convey" a "stacked wafer T" (paragraph 26); corresponding to the "conveying unit that conveys a laminated substrate" in the present invention), "a reforming apparatus 64" that "irradiates the inside of the processing wafer W with laser light to thereby form an edge modified layer and an internal modification layer" (paragraphs 27 and 32); corresponding to the "laser processing unit that forms a modified layer by a laser beam" in the present invention, a "dividing apparatus 63" that "divides the processing wafer W into a first divided wafer W1 and a second divided wafer W2, taking the edge modified layer and the internal modification layer formed by the reforming apparatus 64 as starting points" (paragraphs 27 and 31); corresponding to the "dividing unit that divides the laminated substrate, taking the modified layer as a starting point" in the present invention), and "a control apparatus 70 which serves as a control unit" (paragraph 33); corresponding to the "control unit" in the present invention) for the benefit of separating the processing target and subsequently use the separated processing target.
Therefore, it would have been obvious to one with ordinary skill in the art before the effective filing date of the claimed invention to modify Drescher and use the apparatus taught by Kanemoto for the benefit of separating the processing target and subsequently use the separated processing target.
Regarding Claims 13 – 15, the limitations have been described earlier in rejecting Claims 2 – 4.
Allowable Subject Matter
Claims 5 – 11 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Claims 5 – 11 recite, inter alia, a stacked substrate manufacturing method of further comprising: forming a first device layer on a surface of the thinned first semiconductor substrate; forming, after the forming of the first device layer, a modification layer at an interface between the second semiconductor substrate and the bonding layer or at an inside of the bonding layer with a laser beam penetrating the second semiconductor substrate; and separating the second semiconductor substrate and the bonding layer starting from the modification layer formed at the interface between the second semiconductor substrate and the bonding layer or at the inside of the bonding layer. The Novelty of the methods is the steps used in forming the stacked substrate of several semiconductor devices by utilizing bonding and laser separation. Furthermore, the art of record does not disclose or anticipate the above limitation in combination with other claim elements nor would it be obvious to modify the art of record so as to form a device including the above limitation.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. T\Ishizuka. US 2014/0273400 teaches delaminating bonded wafers by ion implantation method.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ASOK K SARKAR whose telephone number is (571)272-1970. The examiner can normally be reached Mon - Fri; 9:30 AM - 6:30 PM.
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/ASOK K SARKAR/Primary Examiner, Art Unit 2891 December 3, 2025