Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
Amendment filed on 5/11/2026 has been entered. Claims 1 – 4, 16 are amended. Claims 1 – 16 are pending in the present application.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 3 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding Claim 3 ( Currently Amended ), recites: “ … a plurality of the non-through holes is provided, wherein each non-hole in the plurality of the non-through holes … ”. However, based on the context in claim 3, it should be “ … a plurality of the non-through holes is provided, wherein each non-through hole in the plurality of the non-through holes … ” . Please clarify it. For examination purpose, examiner is assuming this section in claim 3 is as suggested above.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1 – 16 are rejected under 35 U.S.C. 103 as being unpatentable over Lin ( Pub. No. US 20150035159 A1 ), hereinafter Lin, in view of Takii ( Pub. No. US 20120119384 A1 ), hereinafter Takii.
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Regarding Independent Claim 1 ( Currently Amended ), Lin teaches a semiconductor device, comprising:
a substrate ( Lin, FIG. 2, 10”; [0012], thinned semiconductor substrate 10” );
a wiring layer ( Lin, FIG. 2, 20, 22, 22T; [0011], inter-metal dielectric (IMD) layers 20; associated metallization layers 22; Top metal contacts 22T ) on a first surface ( Lin, FIG. 1, 10A ) of the substrate ( Lin, FIG. 2, 10” );
a first wiring ( Lin, FIG. 7, 40; [0015], conductive layer 40 ) provided on a second surface ( Lin, FIG. 2, 10B”; [0012], backside 10B'' ) opposite the first surface ( Lin, FIG. 1, 10A ) of the substrate ( Lin, FIG. 2, 10” ); and
a through electrode ( Lin, FIG. 2, FIG. 7, 18; [0010], through-substrate via (TSV) structures 18 ) that connects a second wiring ( Lin, FIG. 2, 22, 22T; [0011], associated metallization layers 22; Top metal contacts 22T ) in the wiring layer ( Lin, FIG. 2, 20, 22, 22T ) and the first wiring ( Lin, FIG. 7, 40 ) and is disposed in a through hole ( Lin, FIG. 2, [0010], through-substrate via (TSV) structures 18 ) that penetrates the substrate ( Lin, FIG. 2, 10” ),
wherein a part of the first wiring ( Lin, FIG. 7, 40 ) has a region in an uneven shape ( Lin, FIG. 7, 40A; [0015], concave portion 40A ),
wherein the uneven shape ( Lin, FIG. 7, 40A ) is a non-through hole ( Lin, FIG. 4, concave surface 18A; [0015], concave portion 40A; [0017], the concave portion 40A located above the concave surface 18A of the TSV structure 18 ) extends into the substrate to a first depth from the second surface of the substrate, and
Lin does not explicitly disclose:
wherein, along a direction parallel to the first surface of the substrate, the through hole is separated from the non-through hole by a portion of the substrate.
However, Takii teaches:
wherein, along a direction parallel to the first surface ( Takii, FIG. 2N, bottom surface of 5 ) of the substrate ( Takii, FIG. 2N, 5; [0113], semiconductor substrate 5 ), the through hole ( Takii, FIG. 2I, 7a; [0114], a through-hole electrode forming-purpose via hole 7a ) is separated from the non-through hole ( Takii, FIG. 2I, 7b; [0116], dummy groove hole portion 7b ) by a portion of the substrate.
Lin and Takii are both considered to be analogous to the claimed invention because they are forming the wiring layers and the through-hole electrodes for semiconductor devices. Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified Lin ( FIG. 2, FIG. 7, 18; [0010], through-substrate via (TSV) structures 18 ) ), to incorporate the teachings of Takii ( FIG. 2I, 7b; [0116], dummy groove hole portion 7b, which is non-through hole ), to implement the non-through hole. Doing so would provide both through-hole and non-through hole, and therefore for a semiconductor device having a through-hole electrode, the design of dummy groove hole portion ( i.e. non-through hole ) can reduce the processing time in the wet etching step ( Takii, [0035] ).
Regarding Claim 2 ( Currently Amended ), Lin and Takii teach the semiconductor device as claimed in claim 1, on which this claim is dependent, Lin and Takii further teach:
wherein the non-through hole ( Lin, FIG. 4, concave surface 18A; [0015], concave portion 40A; [0017], the concave portion 40A located above the concave surface 18A of the TSV structure 18; Takii, FIG. 2I, 7b; [0116], dummy groove hole portion 7b, which is non-through hole ) does not penetrate the substrate ( Lin, FIG. 2, 10” ).
Regarding Claim 3 ( Currently Amended ), Lin and Takii teach the semiconductor device as claimed in claim 2, on which this claim is dependent, Lin and Takii further teach: further comprising:
a plurality ( Lin, FIG. 2, at least two of through-substrate via (TSV) structures 18 18 ) of the non-through holes ( Lin, FIG. 4, concave surface 18A; FIG. 7, concave portion 40A above 18; Takii, FIG. 2I, 7b; [0116], dummy groove hole portion 7b, which is non-through hole ) is provided, wherein each non-through hole in the plurality of the non-through holes extends into the substrate from the second surface ( Lin, FIG. 2, 10B”; [0012], backside 10B''; Takii, FIG. 2N, bottom surface of 5 ) of the substrate to some depth.
Regarding Claim 4 ( Currently Amended ), Lin and Takii teach the semiconductor device as claimed in claim 3, on which this claim is dependent, Lin and Takii further teach:
wherein each non-through hole in the plurality ( Lin, FIG. 2, at least two of through-substrate via (TSV) structures 18 ) of the non-through holes ( Lin, FIG. 4, concave surface 18A; FIG. 7, concave portion 40A; Takii, FIG. 2I, 7b ) extends into the substrate from the second surface of the substrate to a different depth ( Lin , [0014], In an embodiment, the TSV structure 18 can be recessed by, for example, performing a dry etch process using HBr/O2, HBr/Cl2/O2, SF6/CL2, SF6 plasma, or the like. In an embodiment, the distance between the concave surface 18A and the top surface 30A is in the range of about 1000 Å to about 2 µm ).
Regarding Claim 5 ( Previously Presented ), Lin and Takii teach the semiconductor device as claimed in claim 2, on which this claim is dependent, Lin further teaches:
wherein the non-through hole ( Lin, FIG. 4, concave surface 18A; FIG. 7, concave portion 40A ) has a lattice shape( Lin, FIG. 2, at least two of through-substrate via (TSV) structures 18, showing multiple parallel structures ).
Regarding Claim 6 ( Previously Presented ), Lin and Takii teach the semiconductor device as claimed in claim 2, on which this claim is dependent, Lin further teaches:
wherein the non-through hole ( Lin, FIG. 4, concave surface 18A; FIG. 7, concave portion 40A ) is filled with same material as the first wiring (Lin, FIG. 7, 40; [0015], conductive layer 40).
Regarding Claim 7 ( Previously Presented ), Lin and Takii teach the semiconductor device as claimed in claim 2, on which this claim is dependent, Lin further teaches:
wherein the non-through hole ( Lin, FIG. 4, concave surface 18A; FIG. 7, concave portion 40A ).
Lin fails to explicitly disclose:
wherein the non-through hole has a slit shape.
However, Lin teaches:
[0014], Referring to FIG. 4, an etching process is performed to recess the top surface 18T of the TSV structure 18, and thereby the top surface 18T becomes a concave surface 18A.
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified Lin ( FIG. 4, concave surface 18A ) by duplicating the structure in FIG. 4 and overlapping them, and then multiple concave surfaces 18A form a slit shape. Doing so would provide a specific structure for the through-substrate via includes a concave or a convex portion adjacent to the backside of the semiconductor substrate, and therefore the bonding configuration and stacked-die package can be improved.
Regarding Claim 8 ( Previously Presented ), Lin and Takii teach the semiconductor device as claimed in claim 1, on which this claim is dependent, Lin further teaches:
wherein the first wiring ( Lin, FIG. 7, 40; [0015], conductive layer 40 ) is formed in a shape having a step ( Lin, [0015], The concave portion 4A is lower than the surface of the planar portion 40P; [0016], returned signals reflected from the concave portion 40A and the planar portion 40P are read and detected, and the step height is easily aligned by lithographic tools ).
Regarding Claim 9 ( Previously Presented ), Lin and Takii teach the semiconductor device as claimed in claim 1, on which this claim is dependent, Lin further teaches:
wherein a region of the substrate corresponding to the region in the uneven shape ( Lin, FIG. 7, 40A; [0015], concave portion 40A ) of the second surface ( Lin, FIG. 2, 10B”; [0012], backside 10B'' ) of the substrate has a protrusion ( Lin, FIG. 10, 18B; [0020], thereby forming a convex portion 18B of the TSV structures 18 protruding from the backside 10B'' ) in a protruding shape.
Regarding Claim 10 ( Previously Presented ), Lin and Takii teach the semiconductor device as claimed in claim 1, on which this claim is dependent, Lin further teaches:
an insulating film ( Lin, FIG. 3 – FIG. 7, 30; [0013], an isolation film 30 is formed over the backside 10B'' of the thinned semiconductor substrate 10'' to cover the protruding portions of the TSV structures 18; [0015], conductive layer 40 is deposited over the isolation film 30 and the TSV structure 18 ) between the substrate ( Lin, FIG. 2, 10”) and the first wiring ( Lin, FIG. 7, 40 ),
wherein a region of the insulating film (Lin, FIG. 4 – FIG. 7, 30) corresponding to the region in the uneven shape ( Lin, FIG. 7, 40A ) of the second surface ( Lin, FIG. 2, 10B” ) of the substrate has a recess ( Lin, FIG. 7, 30 below 40A ) in a recessed shape.
Regarding Claim 11 ( Previously Presented ), Lin and Takii teach the semiconductor device as claimed in claim 1, on which this claim is dependent, Lin further teaches:
wherein the first wiring ( Lin, FIG. 7, 40 ) and the region in the uneven shape ( Lin, FIG. 7, 40A ) are arranged at a predetermined interval ( Lin, FIG. 2, plurality of through-substrate via (TSV) structures 18 are arranged at a predetermined interval; [0015], The concave portion 40A is lower than the surface of the planar portion 40P ).
Regarding Claim 12 ( Previously Presented ), Lin and Takii teach the semiconductor device as claimed in claim 2, on which this claim is dependent, Lin further teaches:
wherein a size of the non-through hole ( Lin, FIG. 4, concave surface 18A; [0015], concave portion 40A; [0017], the concave portion 40A located above the concave surface 18A of the TSV structure 18 ) is 70% or less ( Lin, the size of 18A in FIG. 4, or the size of 40A in FIG. 7, are less than the size of 18 in FIG. 3 ) of a size of the through electrode ( Lin, FIG. 3, 18 ).
Regarding Claim 13 ( Previously Presented ), Lin and Takii teach the semiconductor device as claimed in claim 7, on which this claim is dependent, Lin further teaches:
wherein a depth of the non-through hole ( Lin, FIG. 4, concave surface 18A; [0015], concave portion 40A; [0017], the concave portion 40A located above the concave surface 18A of the TSV structure 18 ) in the slit shape from the second surface is 50% or less ( Lin, the depth of 18A in FIG. 4, or the depth of 40A in FIG. 7, are less than the depth of 18 in FIG. 3 ) of a depth of the through electrode ( Lin, FIG. 3, 18 ) from the second surface ( Lin, FIG. 2, 10B” ).
Regarding Claim 14 ( Previously Presented ), Lin and Takii teach the semiconductor device as claimed in claim 1, on which this claim is dependent, Lin further teaches:
wherein the uneven shape ( Lin, FIG. 7, 40A; [0015], concave portion 40A ) is formed in such a size that a plating area ( Lin, [0018], The connection element may be any suitable conductive material, such as Cu, Ni, Sn, Au, Ag, solder or the like, and may be formed by any suitable method, including evaporation, electroplating, printing, jetting, stud bumping, direct placement, wire bonding or the like ) per unit area is uniform ( Lin, [0015], a conductive layer 40 is deposited over the isolation film 30 and the TSV structure 18. In an embodiment, the conductive layer 40 is formed by depositing a conformal conductive layer, such as a layer of Al, an Al alloy, W, Cu, Ti, Ta, TiN, TaN, or the like, using CVD or PVD techniques. When the conductive layer 40 is deposited, it replicates the topography of the underlying feature ) in an entire region where the first wiring ( Lin, FIG. 7, 40; [0015], conductive layer 40 ) is disposed.
Regarding Claim 15 ( Previously Presented ), Lin and Takii teach the semiconductor device as claimed in claim 1, on which this claim is dependent, Lin further teaches:
wherein the region in the uneven shape ( Lin, FIG. 7, 40A; [0015], concave portion 40A ) is provided on the first wiring ( Lin, FIG. 7, 40 ) having a large film thickness ( [0016] FIG. 6 illustrates a patterned mask 50 formed over the conductive layer 40 in accordance with an embodiment. The patterned mask 50 defines portions of the conductive layer 40 that will act as conductive pads and/or redistribution lines ).
Regarding Independent Claim 16 ( Currently Amended ), Lin teaches an imaging device (Lin, FIG. 2, 12; [0008], For example, the electrical circuitry 12 may include various N-type metal-oxide semiconductor (NMOS) and/or P-type metal-oxide semiconductor (PMOS) devices, such as transistors, capacitors, resistors, diodes, photo-diodes, ... The functions may include memory structures, processing structures, sensors, amplifiers, power distribution, input/output circuitry) comprising:
a first chip ( FIG. 2, 12 ) on which a solid-state imaging element ( Lin, [0008] ) is formed; and
a second chip ( Lin, FIG. 2, 10”, 18, 20, 22, 22T; [0012], thinned semiconductor substrate 10''; [0011], inter-metal dielectric (IMD) layers 20; associated metallization layers 22; Top metal contacts 22T ) that processes a signal from the first chip ( Lin, FIG. 2, 12, 14; [0009], contacts 14 are formed through an inter-layer dielectric (ILD) layer 16 to provide an electrical contact to the electrical circuitry 12 ),
the second chip ( Lin, FIG. 2, 10”, 18, 20, 22, 22T ) including:
a substrate ( Lin, FIG. 2, 10” );
a wiring layer ( Lin, FIG. 2, 20, 22, 22T; [0011] ) on a first surface ( Lin, FIG. 1, 10A ) of the substrate ( Lin, FIG. 2, 10” );
a first wiring ( Lin, FIG. 7, 40; [0015], conductive layer 40 ) provided on a second surface ( Lin, FIG. 2, 10B”; [0012], backside 10B'' ) opposite the first surface ( Lin, FIG. 1, 10A ) of the substrate ( Lin, FIG. 2, 10 ); and
a through electrode ( Lin, FIG. 2, FIG. 7, 18; [0010], through-substrate via (TSV) structures 18 ) that connects a second wiring ( Lin, FIG. 2, 22, 22T; [0011], associated metallization layers 22; Top metal contacts 22T ) in the wiring layer ( Lin, FIG. 2, 20, 22, 22T ) and the first wiring ( Lin, FIG. 7, 40 ) and is disposed in a through hole ( Lin, [0010], through-substrate via (TSV) structures 18 ) that penetrates the substrate ( Lin, FIG. 2, 10 ),
wherein a part of the first wiring ( Lin, FIG. 7, 40 ) has a region in an uneven shape ( Lin, FIG. 7, 40A; [0015], concave portion 40A ),
wherein the uneven shape ( Lin, FIG. 7, 40A ) is a non-through hole ( Lin, FIG. 4, concave surface 18A; [0015], concave portion 40A; [0017], the concave portion 40A located above the concave surface 18A of the TSV structure 18 ) extends into the substrate to a first depth from the second surface of the substrate, and
Lin does not explicitly disclose:
wherein, along a direction parallel to the first surface of the substrate, the through hole is separated from the non-through hole by a portion of the substrate.
However, Takii teaches:
wherein, along a direction parallel to the first surface ( Takii, FIG. 2N, bottom surface of 5 ) of the substrate ( Takii, FIG. 2N, 5; [0113], semiconductor substrate 5 ), the through hole ( Takii, FIG. 2I, 7a; [0114], a through-hole electrode forming-purpose via hole 7a ) is separated from the non-through hole ( Takii, FIG. 2I, 7b; [0116], dummy groove hole portion 7b ) by a portion of the substrate.
Lin and Takii are both considered to be analogous to the claimed invention because they are forming the wiring layers and the through-hole electrodes for semiconductor devices. Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified Lin ( FIG. 2, FIG. 7, 18; [0010], through-substrate via (TSV) structures 18 ) ), to incorporate the teachings of Takii ( Takii, FIG. 2I, 7b; [0116], dummy groove hole portion 7b, which is non-through hole ), to implement the non-through hole. Doing so would provide both through-hole and non-through hole, and therefore for a semiconductor device having a through-hole electrode, the design of dummy groove hole portion ( i.e. non-through hole ) can reduce the processing time in the wet etching step ( Takii, [0035] ).
Response to Arguments
Applicant’s argument for claims 1 and 16 ( Currently Amended ): page 6, line 2 from bottom, cited “ However, this concave portion 40A of the Lin reference does not extend into the substrate to a first depth from a surface of the substrate as recited by amended claims 1 and 16. In addition, the Lin reference does not disclose a through hole that is separated from a non-through hole by a portion of the substrate. Instead, the concave portion 40A of the Lin reference is directly on top of the TSV 18. Therefore, for at least these reasons, the rejections of the claims as anticipated by or obvious in view of the Lin reference should be reconsidered and withdrawn. ”.
Examiner’s response: Please refer to the Claim Rejections - 35 USC § 103 for claims 1 and 16 (Currently Amended) in this office action, for instance, claim 1, cited “
However, Takii teaches:
wherein, along a direction parallel to the first surface ( Takii, FIG. 2N, bottom surface of 5 ) of the substrate ( Takii, FIG. 2N, 5; [0113], semiconductor substrate 5 ), the through hole ( Takii, FIG. 2I, 7a; [0114], a through-hole electrode forming-purpose via hole 7a ) is separated from the non-through hole ( Takii, FIG. 2I, 7b; [0116], dummy groove hole portion 7b ) by a portion of the substrate.
Lin and Takii are both considered to be analogous to the claimed invention because they are forming the wiring layers and the through-hole electrodes for semiconductor devices. Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified Lin ( FIG. 2, FIG. 7, 18; [0010], through-substrate via (TSV) structures 18 ) ), to incorporate the teachings of Takii ( FIG. 2I, 7b; [0116], dummy groove hole portion 7b, which is non-through hole ), to implement the non-through hole. Doing so would provide both through-hole and non-through hole, and therefore for a semiconductor device having a through-hole electrode, the design of dummy groove hole portion ( i.e. non-through hole ) can reduce the processing time in the wet etching step ( Takii, [0035] ). ”. Therefore, “ a non-through hole extends into the substrate to a first depth from a surface of the substrate as recited by amended claims 1 and 16 ” and “ a through hole that is separated from a non-through hole by a portion of the substrate ” are disclosed by Lin in view of Takii.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Da-Wei Lee whose telephone number is 703-756-1792. The examiner can normally be reached M -̶ F 8:00 am -̶ 6:00 pm.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Marlon Fletcher can be reached at 571-272-2063. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/DA-WEI LEE/Examiner, Art Unit 2817
/MARLON T FLETCHER/Supervisory Primary Examiner, Art Unit 2817
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