Notice of AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The following title is suggested: “Partition Portions And Gaps Alternately Between Wirings In Its Extending Direction”.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-2, 6-7 and 10 are rejected under 35 U.S.C. 103 as being unpatentable over Kraft et al. (US 2014/0367862 A1) in view of Yoda et al. (JP2010258073A).
Regarding independent claim 1: Kraft teaches (e.g., Figs. 1-11) a semiconductor device, comprising:
a semiconductor substrate ([0031]: 1);
a wiring layer ([0033]: 13) including an electrode pad ([0033]: terminal 19 corresponds to a pad based on its structure),
the wiring layer (13) formed on a first surface (upper surface of the substrate 1) of the semiconductor substrate (1);
a redistribution layer ([0033]: wiring 9 functions as a redistribution layer because it redistribute or relocate the input/output contact of the device using layer 9) including wiring (13) electrically connected to the electrode pad ([0033]: terminal 19 corresponds to a pad based on its structure) via a via ([0033]: conductive portion in the trench 3),
the redistribution layer ([0033]: 9) formed on a second surface side (bottom side) opposite to the first surface of the semiconductor substrate (1);
a protective film ([0063]: 8) formed on a surface on a side opposite to the semiconductor substrate in the redistribution layer (Fig. 11; [0053]: 9); and
Kraft does not expressly teach
a partition formed by an insulating material, the partition arranged between pieces of wiring in the redistribution layer,
wherein the partition and a void are alternately formed between the pieces of wiring in a direction in which the wiring extends.
Yoda teaches (Figs. 14, 23 and 25 combined for clarification purposes; selected Figures include Fig. 23 and Fig. 14) a semiconductor device, comprising:
a partition ([0120]-[0121] and [0123]: 23a/41) formed by an insulating material ([0120]-[0121] and [0123]), the partition arranged between pieces of wiring ([0121] and [0123]: 21) in an interconnect layer ([0091]-[0092]: 20),
wherein the partition ([0121] and [0123]: 23a/41) and a void ([0121] and [0123]: 23b) are alternately formed between pieces of wiring ([0121] and [0123]: 21) in a direction in which the wiring extends (Fig. 25; [0121] and [0123]: 21).
It would have been obvious to a person of ordinary skill in the art at the time of the effective filing date to include in the device of Kraft, the partition formed by an insulating material, the partition arranged between pieces of wiring, wherein the partition and a void are alternately formed between the pieces of wiring in a direction in which the wiring extends, as taught by Yoda, for the benefits of reducing heat concentration in the device layer during the operation of the device and at the same time facilitating heat transfer away from the device by using the partition layer (Yoda: [0054]).
Regarding claim 2: Kraft and Yoda teach the claim limitation of the semiconductor device according to claim 1, on which this claim depends,
wherein the insulating material is any one of SiOx, SiOxNy, and an insulating organic resin (Yoda: [0120]-[0121] and [0123]: 23a/41 comprises 23a comprising a SiOx and a resist layer 41 considered an insulating organic resin).
Regarding claim 6: Kraft and Yoda teach the claim limitation of the semiconductor device according to claim 1, on which this claim depends,
wherein the partition has a rectangular parallelepiped shape (Yoda: [0120]-[0121] and [0123]: 23a/41 has a rectangular parallelepiped shape).
Regarding claim 7: Kraft and Yoda teach the claim limitation of the semiconductor device according to claim 1, on which this claim depends,
wherein the void Yoda: ([0121] and [0123]: 23b) is a hole formed in an insulating material (Yoda: [0121] and [0123]: 23) that enters between the pieces of wiring (Yoda: [0121] and [0123]: 21).
Regarding independent claim 10: Kraft teaches (e.g., Figs. 1-11) a semiconductor device manufacturing methods comprising:
alternately forming, in a semiconductor substrate ([0031]: 1) on a first surface (upper surface) of which a wiring layer ([0033]: 13) including an electrode pad ([0033]: terminal 19 corresponds to a pad based on its structure) is formed and on a second surface side (bottom surface) of which a redistribution layer ([0033]: wiring 9 functions as a redistribution layer because it redistribute or relocate the input/output contact of the device using layer 9) including wiring (13) electrically connected to the electrode pad ([0033]: terminal 19 corresponds to a pad based on its structure) via a via ([0033]: conductive portion in the trench 3), is formed, the second surface side opposite to the first surface;
Kraft does not expressly teach
a partition and a void in a direction in which the wiring extends between pieces of wiring in the redistribution layer.
Yoda teaches (Figs. 14, 23 and 25 combined for clarification purposes; selected Figures include Fig. 23 and Fig. 14) a semiconductor device, comprising:
a partition ([0120]-[0121] and [0123]: 23a/41) and a void ([0121] and [0123]: 23b) in a direction in which the wiring extends (Fig. 25; [0121] and [0123]: 21) between pieces of wiring ([0121] and [0123]: 21).
It would have been obvious to a person of ordinary skill in the art at the time of the effective filing date to include in the device of Kraft, the partition and the void in a direction in which the wiring extends between pieces of wiring, as taught by Yoda, for the benefits of reducing heat concentration in the device layer during the operation of the device and at the same time facilitating heat transfer away from the device by using the partition layer (Yoda: [0054]).
Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over Kraft et al. (US 2014/0367862 A1) in view of Yoda et al. (JP2010258073A) as applied above and further in view of Shin et al. (US 2019/0148439 A1).
Regarding claim 9: Kraft and Yoda teach the claim limitation of the semiconductor device according to claim 1, on which this claim depends,
wherein photoelectric conversion elements that perform photoelectric conversion (Kraft: [0055]: an applicable sensor device inherently include photoelectric conversion elements) are formed in the semiconductor substrate.
Kraft as modified by Yoda does not expressly teach that the photoelectric conversion elements are formed in a two-dimensional array in the semiconductor substrate.
Shin teaches (e.g., Figs. 1-2A) a semiconductor device comprising a semiconductor substrate ([0031]: 110) and photoelectric conversion elements ([0030]-[0031]: 120);
Shin further teaches photoelectric conversion elements ([0030]-[0031]: 120) are formed in a two-dimensional array (Fig. 1; photoelectric conversion elements 120 are formed in a two-dimensional array, as shown in Fig. 1) in the semiconductor substrate (Figs. 1-2A; [0030]-[0031]: 110).
It would have been obvious to a person of ordinary skill in the art at the time of the effective filing date to include in the device of Kraft, the photoelectric conversion elements formed in a two-dimensional array in the semiconductor substrate, as taught by Shin, for the benefits of increasing the imager device sensitivity by disposing the photoelectric conversion elements in a tight array or matrix.
Claim 11 is rejected under 35 U.S.C. 103 as being unpatentable over Kraft et al. (US 2014/0367862 A1) in view of Yoda et al. (JP2010258073A) as applied above and further in view of Oota et al. (US 2020/0013821 A1).
Regarding claim 11: Kraft and Yoda teach the claim limitation of the semiconductor device manufacturing method according to claim 10, on which this claim depends,
wherein the void is formed by forming a protective film (Yoda: [0120]-[0121] and [0123]: 23a/41);
Kraft as modified by Yoda does not expressly teach a spin coating method.
Oota teaches (e.g., Figs. 2-4) a method comprising forming a protective film spin coating ([0087] and [0135]).
It would have been obvious to a person of ordinary skill in the art at the time of the effective filing date to include in the method of Kraft as modified by Yoda, the method of forming a protective layer by spin coating method, as taught by Oota, for the benefits, of controlling the formation process by using a flowable material that can easily flow to fill the desired layer or structure having a desired thickness and strength.
Allowable Subject Matter
Claims 3-5 and 8 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claim 3: the cited prior art of record, either singly or in proper combination, does not teach or make obvious, along with the other claimed features, a semiconductor device comprising:
“ wherein two pieces of wiring having a first inter-wiring distance and two pieces of wiring having a second inter-wiring distance are formed in the redistribution layer,
the first inter-wiring distance is made shorter than the second inter-wiring distance, and an interval between partitions arranged between the two pieces of wiring having the first inter-wiring distance, the partitions adjacent to each other in a direction in which the wiring extends is made larger than an interval between the partitions arranged between the two pieces of wiring having the second inter-wiring distance, the partitions adjacent to each other in a direction in which the wiring extends”.
Claim 4 depends from claim 3, and therefore, is allowable for the same reason as claim 3.
Regarding claim 5: the cited prior art of record, either singly or in proper combination, does not teach or make obvious, along with the other claimed features, a semiconductor device comprising:
“wherein the partition has a cylindrical shape an axial direction of which coincides with a stacking direction of the redistribution layer with respect to the semiconductor substrate”.
Regarding claim 8: the cited prior art of record, either singly or in proper combination, does not teach or make obvious, along with the other claimed features, a semiconductor device comprising:
“wherein an insulating resin film is formed between the semiconductor substrate and the redistribution layer, and the void is formed as a space reaching an inside of the insulating resin film”.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to HERVE-LOUIS Y ASSOUMAN whose telephone number is (571)272-2606. The examiner can normally be reached M-F: 08:30 AM-5:30 PM.
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/HERVE-LOUIS Y ASSOUMAN/ Examiner, Art Unit 2812